There is, I think, something ethereal about i —the square root of minus one. I remember first hearing about it at school. It seemed an odd beast at that time—an intruder hovering on the edge of reality.

Usually familiarity dulls this sense of the bizarre, but in the case of i it was the reverse: over the years the sense of its surreal nature intensified. It seemed that it was impossible to write mathematics that described the real world in …

I and i

On robust estimation of the location parameter

Aspect] is a simple and practical aspect-oriented extension to Java With just a few new constructs, AspectJ provides support for modular implementation of a range of crosscutting concerns. In AspectJ's dynamic join point model, join points are well-defined points in the execution of the program; pointcuts are collections of join points; advice are special method-like constructs that can be attached to pointcuts; and aspects are modular units of crosscutting implementation, comprising pointcuts, advice, and ordinary Java member declarations. AspectJ code is compiled into standard Java bytecode. Simple extensions to existing Java development environments make it possible to browse the crosscutting structure of aspects in the same kind of way as one browses the inheritance structure of classes. Several examples show that AspectJ is powerful, and that programs written using it are easy to understand.

An overview of AspectJ

Deep neural networks (DNNs) are currently widely used for many artificial intelligence (AI) applications including computer vision, speech recognition, and robotics. While DNNs deliver state-of-the-art accuracy on many AI tasks, it comes at the cost of high computational complexity. Accordingly, techniques that enable efficient processing of DNNs to improve energy efficiency and throughput without sacrificing application accuracy or increasing hardware cost are critical to the wide deployment of DNNs in AI systems. This article aims to provide a comprehensive tutorial and survey about the recent advances toward the goal of enabling efficient processing of DNNs. Specifically, it will provide an overview of DNNs, discuss various hardware platforms and architectures that support DNNs, and highlight key trends in reducing the computation cost of DNNs either solely via hardware design changes or via joint hardware design and DNN algorithm changes. It will also summarize various development resources that enable researchers and practitioners to quickly get started in this field, and highlight important benchmarking metrics and design considerations that should be used for evaluating the rapidly growing number of DNN hardware designs, optionally including algorithmic codesigns, being proposed in academia and industry. The reader will take away the following concepts from this article: understand the key design considerations for DNNs; be able to evaluate different DNN hardware implementations with benchmarks and comparison metrics; understand the tradeoffs between various hardware architectures and platforms; be able to evaluate the utility of various DNN design techniques for efficient processing; and understand recent implementation trends and opportunities.

Efficient Processing of Deep Neural Networks: A Tutorial and Survey

The objective of this paper is to give a comprehensive introduction to applied cryptography with an engineer or computer scientist in mind. The emphasis is on the knowledge needed to create practical systems which supports integrity, confidentiality, or authenticity. Topics covered includes an introduction to the concepts in cryptography, attacks against cryptographic systems, key use and handling, random bit generation, encryption modes, and message authentication codes. Recommendations on algorithms and further reading is given in the end of the paper. This paper should make the reader able to build, understand and evaluate system descriptions and designs based on the cryptographic components described in the paper.

[서평]「Applied Cryptography」

/pdf/field-programmable-logic-and-applications-3nehje7jrg.pdf

Field-Programmable Logic and Applications

Commonly used in software design, assertions are statements placed into a design to ensure that its behavior matches that expected by a designer. Although assertions apply equally to hardware design, they are typically supported only for logic simulation, and discarded prior to physical implementation. We propose a new hardware design language-agnostic language for describing latency-insensitive assertions and novel methods to add such assertions transparently to an already placed-and-routed circuit without affecting the existing design. We also describe how this language and associated methods can be used to implement semi-transparent exception handling. The key to this paper is that by treating hardware assertions and exceptions as being oblivious or less sensitive to latency, assertion logic need only use spare FPGA resources. We use network-flow techniques to route necessary signals to assertions via spare flip-flops, eliminating any performance degradation, even on large designs (92% of slices in one test). Experimental evaluation shows zero impact on critical-path delay, even on large benchmarks operating above 200 MHz, at the cost of a small power penalty.

/pdf/transparent-in-circuit-assertions-for-fpgas-5145b5qod0.pdf

Transparent In-Circuit Assertions for FPGAs

This paper proposes a novel approach for design space exploration by characterizing hardware sharing based on the notion of a partition in set theory. Related designs with different degrees of hardware sharing can be captured concisely by a Hasse diagram, high-lighting designs with shared building blocks. Hardware sharing can be implemented in various ways, such as component multiplexing, instruction-set processors, or run-time reconfiguration. We illustrate how the proposed approach can be applied to exploring the design space for FPGA implementations of JPEG image compression.

Partition-based exploration for reconfigurable JPEG designs

A systematic approach to design space exploration of customisable options for multi-processor architectures is presented. This approach is used to explore a parameterisable system model as a part of a novel exploration tool. Architecture trends are analysed through the variation of prefabrication choice of number of processing elements (PEs) and cache size. Of note, is the relationship between multi-threading and off-chip memory access. This is shown to reduce performance by up to five times for a decimation case study. From the analysis of architecture trends, a post-fabrication choice of processing pattern is shown to provide up to three times improvement for a negligible area cost. In verification, the system model mimics the performance of sample graphics processors. This is achieved with a run time of only five minutes for a decimation case study with a model setup of eight processing elements and 16 KB cache.

Systematic design space exploration for customisable multi-processor architectures

The design of a new FPGA architecture.- Migration of a dual granularity globally interconnected PLD architecture to a 0.5? TLM process.- Self-timed FPGA systems.- The XC6200 FastMap(TM) processor interface.- The Teramac configurable compute engine.- Telecommunication-oriented FPGA and dedicated CAD system.- A configurable logic processor for machine vision.- Extending DSP-boards with FPGA-based structures of interconnection.- High-speed region detection and labeling using an FPGA-based custom computing platform.- Using FPGAS as control support in MIMD executions.- Customised hardware based on the REDOC III algorithm for high performance data ciphering.- Using reconfigurable hardware to speed up product development and performance.- Creation of hardware objects in a reconfigurable computer.- Rapid hardware prototyping of Digital Signal Processing systems using Field Programmable Gate Arrays.- Delay minimal mapping of RTL structures onto LUT based FPGAs.- Some notes on power management on FPGA-based systems.- An automatic technique for realising user interaction processing in PLD based systems.- Proper use of hierarchy in HDL-based high density FGPA design.- Compiling regular arrays onto FPGAs.- Compiling Ruby into FPGAs.- The CSYN verilog compiler and other tools.- A VHDL design methodology for FPGAs.- VHDL-based rapid hardware prototyping using FPGA technology.- Integer programming for partitioning in software oriented codesign.- Test standard serves dual role as on-board programming solution.- Advanced method for industry related education with an FPGA design self-learning kit.- FPGA implementation of a rational adder.- FPLD-implementation of computations over finite fields GF(2m) with applications to error control coding.- Implementation of Fast Fourier Transforms and Discrete Cosine Transforms in FPGAs.- Implementation of a 2-D fast Fourier transform on an FPGA-based custom computing machine.- An assessment of the suitability of FPGA-based systems for use in digital signal processing.- An FPGA prototype for a multiplierless FIR filter built using the logarithmic number system.- Bit-serial FIR filters with CSD coefficients for FPGAs.- A self-validating temperature sensor implemented in FPGAs.- Developing interface libraries for reconfigurable data acquisition boards.- Prototype generation of application specific embedded controllers for microsystems.- A hardware genetic algorithm for the traveling salesman problem on Splash 2.- Modular architecture for real-time astronomical image processing with FPGA.- A programmable I/O system for real-time AC drive control applications.- Reconfigurable logic for fault tolerance.- Supercomputing with reconfigurable architectures.- Automatic synthesis of parallel programs targeted to dynamically reconfigurable logic arrays.- Prototyping environment for dynamically reconfigurable logic.- Implementation approaches for reconfigurable logic applications.- Use of reconfigurability in variable-length code detection at video rates.- Classification and performance of reconfigurable architectures.

Wayne Luk

Papers

Field-Programmable Logic and Applications

Transparent In-Circuit Assertions for FPGAs

Partition-based exploration for reconfigurable JPEG designs

Systematic design space exploration for customisable multi-processor architectures

Field-Programmable Logic and Applications: 5th International Workshop, FPL '95, Oxford, United Kingdom, August 29 - September 1, 1995. Proceedings