Wayne Luk

TL;DR: A framework for generating parameterised high-performance IP library cores from high level descriptions based around the Quartz language which provides advanced features such as polymorphism, overloading, higher-order combinators and formal reasoning while supporting precise and flexible control of layout for efficient FPGA design and compiling into parameterised VHDL libraries is presented.

TL;DR: The EXTRA project creates a new and flexible exploration platform for developing reconfigurable architectures, design tools and HPC applications with run-time reconfiguration built-in as a core fundamental feature instead of an add-on.

TL;DR: The extensions are based on those of Occam 2, a language related to Handel-C, and it is shown that they can implement the basic real-time idioms of timed wait and timeout.

TL;DR: PolSCA as mentioned in this paper is a compiler framework that improves polyhedral HLS workflow by automatic code transformation, decomposing a design before polyhedral optimization to balance code complexity and parallelism, while revising memory interfaces of polyhedral-transformed code to make partitioning explicit for HLS tools.

TL;DR: This work includes a high-level approach to adding assertions and exceptions to a design, a concrete implementation for Maxeler streaming designs, and an evaluation, which shows low overhead for supporting assertions and exception in hardware design targeting FPGAs.