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Wayne Luk
Researcher at Imperial College London
Publications - 737
Citations - 13643
Wayne Luk is an academic researcher from Imperial College London. The author has contributed to research in topics: Field-programmable gate array & Reconfigurable computing. The author has an hindex of 54, co-authored 703 publications receiving 12517 citations. Previous affiliations of Wayne Luk include Fudan University & University of London.
Papers
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Proceedings ArticleDOI
Efficient Structured Pruning and Architecture Searching for Group Convolution
Ruizhe Zhao,Wayne Luk +1 more
TL;DR: The authors formulate group convolution pruning as finding the optimal channel permutation to impose structural constraints and solve it efficiently by heuristics, and apply local search to explore group configuration based on estimated pruning cost to maximise test accuracy.
Proceedings ArticleDOI
Wave-pipelined signaling for on-FPGA communication
TL;DR: This issue is addressed by presenting a new wave-pipelined signaling scheme to achieve high-throughput communication in FPGA and the throughput and power consumption of a wave- pipelined link have been derived analytically and compared to the conventional synchronous link.
Journal ArticleDOI
Systolic recursive filters
Wayne Luk,Geraint Jones +1 more
TL;DR: Two systolic arrays for recursive digital filtering are presented and both have a rectangular structure and produce output for a particular computation in consecutive cycles.
Proceedings ArticleDOI
Global interconnections in FPGAs: modeling and performance analysis
TL;DR: A new model for global routings in FPGAs shows that interconnection throughput can be significantly increased using wave-pipelined signaling instead of the conventional delay-based synchronous approach, as has been demonstrated in the FPGA experiments.
Proceedings ArticleDOI
Knowledge Transfer in Automatic Optimisation of Reconfigurable Designs
TL;DR: A novel approach for automatic optimisation of reconfigurable design parameters based on knowledge transfer is presented, capable of achieving up to 35% reduction in optimisation time in producing designs with similar performance, compared to alternative optimisation methods.