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Wayne Luk
Researcher at Imperial College London
Publications - 737
Citations - 13643
Wayne Luk is an academic researcher from Imperial College London. The author has contributed to research in topics: Field-programmable gate array & Reconfigurable computing. The author has an hindex of 54, co-authored 703 publications receiving 12517 citations. Previous affiliations of Wayne Luk include Fudan University & University of London.
Papers
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Book ChapterDOI
Automating Customisation of Floating-Point Designs
TL;DR: A method for customising the representation of floating-point numbers that exploits the flexibility of re-configurable hardware and can produce hardware that is smaller and faster when compared with a design adopting the reference representation.
Proceedings ArticleDOI
F-E3D: FPGA-based Acceleration of an Efficient 3D Convolutional Neural Network for Human Action Recognition
Hongxiang Fan,Cheng Luo,Chenglong Zeng,Martin Ferianc,Zhiqiang Que,Shuanglong Liu,Xinyu Niu,Wayne Luk +7 more
TL;DR: This paper adopts an algorithm-hardware co-design method by proposing an efficient 3D CNN building unit called 3D-1 bottleneck residual block (3D- 1 BRB) at the algorithm level, and a corresponding FPGA-based hardware architecture called F-E3D at the hardware level.
Book ChapterDOI
Pipeline morphing and virtual pipelines
TL;DR: This work shows how morphing can be applied to linear and mesh pipelines at both word-level and bit-level, and explains how this method can be implemented using Xilinx 6200 FPGAs.
Journal ArticleDOI
The LUT-SR Family of Uniform Random Number Generators for FPGA Architectures
David B. Thomas,Wayne Luk +1 more
TL;DR: This paper describes a type of FPGA RNG called a LUT-SR RNG, which takes advantage of bitwise xor operations and the ability to turn lookup tables (LUTs) into shift registers of varying lengths, with quality comparable to the best software generators.
Book ChapterDOI
Hardware acceleration of genetic sequence alignment
TL;DR: This paper explores the use of reconfigurable hardware to accelerate the short read mapping problem, and finds that an implementation targeting the MaxWorkstation performs considerably faster and more energy efficient than current CPU and GPU based software aligners.