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Wayne Luk
Researcher at Imperial College London
Publications - 737
Citations - 13643
Wayne Luk is an academic researcher from Imperial College London. The author has contributed to research in topics: Field-programmable gate array & Reconfigurable computing. The author has an hindex of 54, co-authored 703 publications receiving 12517 citations. Previous affiliations of Wayne Luk include Fudan University & University of London.
Papers
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Proceedings ArticleDOI
Hardware Acceleration for Machine Learning
TL;DR: An approach to enhance the performance of machine learning applications based on hardware acceleration based on parameterised architectures designed for Convolutional Neural Network and Support Vector Machine, and the associated design flow common to both is presented.
Proceedings ArticleDOI
An FPGA implementation of the simplex algorithm
TL;DR: This work aims to accelerate the Simplex algorithm by proposing a novel parameterizable hardware implementation of the algorithm on an FPGA, demonstrating a speedup of up to 20 times over a highly optimized commercial software implementation running on a 3.4GHz Pentium 4 processor.
Proceedings ArticleDOI
Ramethy: Reconfigurable Acceleration of Bisulfite Sequence Alignment
TL;DR: The design, Ramethy (Reconfigurable Acceleration of METHYlation data analysis), performs alignment of short reads with up to two mismatches and consumes over an order of magnitude lower energy while having accuracy identical to soap2 and soap3-dp, making it a strong candidate for integration into bioinformatics pipelines.
Journal ArticleDOI
An Analytical Model Relating FPGA Architecture to Logic Density and Depth
TL;DR: The model relates the lookup-table size, the cluster size, and the number of inputs per cluster to the amount of logic that can be packed into each lookup- table and cluster, the number and depth of the circuit after technology mapping and clustering.
Journal ArticleDOI
HArtes: Hardware-Software Codesign for Heterogeneous Multicore Platforms
Koen Bertels,Vlad-Mihai Sima,Y. Yankova,Georgi Kuzmanov,Wayne Luk,G Coutinho,Fabrizio Ferrandi,Christian Pilato,Marco Lattuada,Donatella Sciuto,A. Michelotti +10 more
TL;DR: The hArtes toolchain this paper provides the option of automatic or semi-automatic support for mapping the application to the most appropriate hardware component, which can be used to reduce development time.