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Wayne Luk

Researcher at Imperial College London

Publications -  737
Citations -  13643

Wayne Luk is an academic researcher from Imperial College London. The author has contributed to research in topics: Field-programmable gate array & Reconfigurable computing. The author has an hindex of 54, co-authored 703 publications receiving 12517 citations. Previous affiliations of Wayne Luk include Fudan University & University of London.

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Using Agent-Based Modelling to Evaluate the Impact of Algorithmic Curation on Social Media

TL;DR: This research provides useful insights into the impact of curation algorithms on how information propagates and on content diversity on social media and shows how agent-based modelling can reveal specific properties ofCuration algorithms, which can be used in improving such algorithms.
Proceedings ArticleDOI

A Unified Approach for Managing Heterogeneous Processing Elements on FPGAs

Stewart Denholm, +1 more
TL;DR: In this article , a call-and-response approach to computation allows for different processing element implementations, connections, latencies and non-deterministic behaviour. But it does not address the problem of managing all available processing elements, which can unbalance parallel pipelines and complicate development.
Proceedings ArticleDOI

Resource-Efficient Designs Using an Aspect-Oriented Approach

TL;DR: A novel approach, based on an aspect-oriented language called LARA, that enables systematic coding and reuse of optimisation strategies that address such non-functional requirements, and can be used to automatically produce a range of designs with different trade-offs in resource usage and numerical accuracy according to a given LARA-based strategy.
Posted Content

Extending the RISC-V ISA for exploring advanced reconfigurable SIMD instructions

TL;DR: In this article, a set of vector instruction types for exploring custom SIMD instructions in a softcore is presented, allowing simultaneous access to a relatively high number of operands, reducing the instruction count where applicable.
Proceedings ArticleDOI

Accelerating Financial Market Server through Hybrid List Design (Abstract Only)

TL;DR: A CPU-FPGA hybrid list design to accelerate financial market servers that achieve microsecond-level latencies and significantly reducing the latency from 100+ microseconds to 2 microseconds is proposed, gaining a speedup of 50x.