Y
Y. Okuno
Researcher at Panasonic
Publications - 6
Citations - 171
Y. Okuno is an academic researcher from Panasonic. The author has contributed to research in topics: CMOS & NMOS logic. The author has an hindex of 4, co-authored 6 publications receiving 168 citations.
Papers
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Proceedings ArticleDOI
Ultra low-EOT (5 Å) gate-first and gate-last high performance CMOS achieved by gate-electrode optimization
Lars-Ake Ragnarsson,Zilan Li,J. Tseng,Tom Schram,E. Rohr,Moon Ju Cho,Thomas Kauerauf,Thierry Conard,Y. Okuno,Bertrand Parvais,Philippe Absil,Serge Biesemans,T. Y. Hoffmann +12 more
TL;DR: In this article, a zero interface layer and optimized gate-electrode are used to achieve ultra low EOT and Tinv values of ∼5 A and ∼8 A respectively for both n and pMOS devices.
Journal ArticleDOI
Stress Memorization Technique—Fundamental Understanding and Low-Cost Integration for Advanced CMOS Technology Using a Nonselective Process
C. Ortolland,Y. Okuno,Peter Verheyen,Christoph Kerner,C. Stapelmann,Marc Aoulaiche,Naoto Horiguchi,T. Y. Hoffmann +7 more
TL;DR: A novel low-cost solution for a maskless SMT integration into advanced CMOS technologies is proposed, and additional device results examining the compatibility of SMT with fully silicided and metal inserted polysilicon gates are presented.
Proceedings Article
Optimized ultra-low thermal budget process flow for advanced High-K / Metal gate first CMOS using laser-annealing technology
C. Ortolland,Lars-Ake Ragnarsson,Paola Favia,O. Richard,Christoph Kerner,Thomas Chiarella,Erik Rosseel,Y. Okuno,A. Akheyar,J. Tseng,J.-L. Everaert,Tom Schram,Stefan Kubicek,Marc Aoulaiche,Moon Ju Cho,Philippe Absil,Serge Biesemans,T. Y. Hoffmann +17 more
TL;DR: In this paper, the first time the successful integration of laser-only annealing in a high-k / metal gate first process flow with functional ring oscillators was presented.
Proceedings ArticleDOI
Strain enhanced low-V T CMOS featuring La/Al-doped HfSiO/TaC and 10ps invertor delay
Stefan Kubicek,Tom Schram,E. Rohr,Vasile Paraschiv,Rita Vos,Marc Demand,Christoph Adelmann,Thomas Witters,Laura Nyns,Annelies Delabie,L.-A. Ragnarsson,Thomas Chiarella,Christoph Kerner,Abdelkarim Mercha,Bertrand Parvais,Marc Aoulaiche,C. Ortolland,Hao Yu,Anabela Veloso,Liesbeth Witters,R. Singanamalla,Thomas Kauerauf,Stephan Brus,Christa Vrancken,V.S. Chang,S.Z. Chang,R. Mitsuhashi,Y. Okuno,A. Akheyar,H.-J. Cho,J.C. Hooker,Barry O'Sullivan,S. Van Elshocht,K. De Meyer,Malgorzata Jurczak,Philippe Absil,Serge Biesemans,T. Y. Hoffmann +37 more
TL;DR: Kubicek et al. as mentioned in this paper proposed a blanket SMT process that does not require a photo to protect the pMOS by selecting a hydrogen-rich SiN film.
Proceedings ArticleDOI
Junction anneal sequence optimization for advanced high-k / metal gate CMOS technology
C. Ortolland,Lars-Ake Ragnarsson,Christoph Kerner,Thomas Chiarella,Erik Rosseel,Y. Okuno,Paola Favia,O. Richard,J.-L. Everaert,Tom Schram,Stefan Kubicek,Philippe Absil,Serge Biesemans,R. Schreutelkamp,T. Y. Hoffmann +14 more
TL;DR: In this paper, the junction anneal strategy (by spike and/or laser) for advanced technology nodes with Hk/MG and high-k capping film to control the eWF was studied.