Yue Hu

TL;DR: In this article, the authors leverage the superior mobility, low threshold voltage and NBTI of cSiGe channels in high-performance (HP) and low power (LP) high-к/metal gate (HKMG) logic MOSFETs with multiple oxides utilizing dual channels for nFET and pFET.

TL;DR: In this article, the benefits, trade-offs and limitations of fin width scaling on logic and SRAM device characteristics were investigated, and it was found that there is a critical fin width (Wc) at ∼4nm.

TL;DR: In this paper, a method of forming an integrated circuit includes providing a base substrate having an embedded electrical contact disposed therein, and a recess is etched through the interlayer dielectric over the embedded electrical contacts.

TL;DR: In this paper, the authors proposed a method to prevent contact encroachment in a semiconductor device by inserting a dielectric liner in a contact trench and then etching the contact trench channel the remainder of the way to the source-drain region.

TL;DR: In this paper, the first and second dummy gates with spacers at opposite sides of the first dummy gate were constructed on a substrate and a silicon cap on each of the eSiGe and raised source/drain regions.