E
Eric C. Harley
Researcher at IBM
Publications - 29
Citations - 368
Eric C. Harley is an academic researcher from IBM. The author has contributed to research in topics: Semiconductor & Epitaxy. The author has an hindex of 10, co-authored 29 publications receiving 362 citations. Previous affiliations of Eric C. Harley include GlobalFoundries.
Papers
More filters
Proceedings ArticleDOI
A manufacturable dual channel (Si and SiGe) high-k metal gate CMOS technology with multiple oxides for high performance and low power applications
Siddarth A. Krishnan,Unoh Kwon,Naim Moumen,Matthew W. Stoker,Eric C. Harley,Stephen W. Bedell,Deleep R. Nair,B. Greene,William K. Henson,Murshed M. Chowdhury,D.P. Prakash,Ernest Y. Wu,Dimitris P. Ioannou,Eduard A. Cartier,Myung-Hee Na,S. Inumiya,Kevin McStay,Lisa F. Edge,Ryosuke Iijima,Jin Cai,Martin M. Frank,M. Hargrove,Dechao Guo,Andreas Kerber,Hemanth Jagannathan,Takashi Ando,Joseph F. Shepard,Shahab Siddiqui,Min Dai,Huiming Bu,J. Schaeffer,Jaeger Daniel,Kathy Barla,Thomas A. Wallner,S. Uchimura,Y. Lee,Gauri Karve,Sufi Zafar,Dominic J. Schepis,Yun-Yu Wang,Ricardo A. Donaton,S. Saroop,P. Montanini,Yue Liang,James H. Stathis,Richard Carter,Rohit Pal,Vamsi Paruchuri,H. Yamasaki,J-H Lee,Martin Ostermayr,J.-P. Han,Yue Hu,Michael A. Gribelyuk,Dae-Gyu Park,X. Chen,Srikanth Samavedam,Shreesh Narasimha,Paul D. Agnello,Mukesh Khare,R. Divakaruni,Vijay Narayanan,Michael P. Chudzik +62 more
TL;DR: In this article, the authors leverage the superior mobility, low threshold voltage and NBTI of cSiGe channels in high-performance (HP) and low power (LP) high-к/metal gate (HKMG) logic MOSFETs with multiple oxides utilizing dual channels for nFET and pFET.
Patent
Multigate finFETs with epitaxially-grown merged source/drains
TL;DR: In this paper, a multi-gate fin FET with epitaxially-grown merged source/drains is proposed, which consists of a plurality of semiconductor fin regions joined by a plurality inter-fin semiconductor regions.
Proceedings ArticleDOI
High-performance nMOSFET with in-situ phosphorus-doped embedded Si:C (ISPD eSi:C) source-drain stressor
B. Yang,R. Takalkar,Zhibin Ren,L. Black,Abhishek Dube,J.W. Weijtmans,James Chingwei Li,Jeffrey B. Johnson,Johnathan E. Faltermeier,Anita Madan,Z. Zhu,A. Turansky,Guangrui Xia,A. Chakravarti,R. Pal,K.K. Chan,Alexander Reznicek,Thomas N. Adam,J. P. de Souza,Eric C. Harley,Brian J. Greene,A. Gehring,M. Cai,D. Aime,S. Sun,H. Meer,Judson R. Holt,David Theodore,Stefan Zollner,Paul A. Grudowski,D. K. Sadana,Dae-Gyu Park,Dan Mocuta,Dominic J. Schepis,Edward P. Maciejewski,Scott Luning,John G. Pellerin,Effendi Leobandung +37 more
TL;DR: In this paper, embedded Si:C (eSi:C) was demonstrated to be a superior nMOSFET stressor compared to SMT or tensile liner (TL) stressors.
Patent
METHODS OF INTEGRATING REVERSE eSiGe ON NFET AND SiGe CHANNEL ON PFET, AND RELATED STRUCTURE
Eric C. Harley,Judson R. Holt,Dominic J. Schepis,Michael D. Steigerwalt,Linda Black,Rick Carter +5 more
TL;DR: In this article, reverse embedded silicon germanium (SiGe) was integrated on an NFET and SiGe channel on a PFET, and a related structure was disclosed.
Proceedings ArticleDOI
Gate length scaling and high drive currents enabled for high performance SOI technology using high-κ/metal gate
K. Henson,Huiming Bu,Myung-Hee Na,Yue Liang,Unoh Kwon,Siddarth A. Krishnan,James K. Schaeffer,Rashmi Jha,Naim Moumen,R. Carter,C. DeWan,Ricardo A. Donaton,Dechao Guo,M. Hargrove,Wei He,R. Mo,Ravikumar Ramachandran,Karthik Ramani,Kathryn T. Schonenberg,Y. Tsang,X. Wang,Michael A. Gribelyuk,W. Yan,Joseph F. Shepard,Eduard A. Cartier,Martin M. Frank,Eric C. Harley,R. Arndt,R. Knarr,Todd Bailey,B. Zhang,Keith Kwong Hon Wong,Troy L. Graves-Abe,E. Luckowski,D.-G. Park,Vijay Narayanan,Michael P. Chudzik,Mukesh Khare +37 more
TL;DR: In this article, high-k/metal gate stacks have been fabricated using a gate-first process flow and conventional stressors at gate lengths of 25 nm, highlighting the scalability of this approach for high performance SOI CMOS technology.