Showing papers in "IEEE Design & Test of Computers in 2012"
TL;DR: A holistic approach to reducing the energy footprint of large commercial buildings is proposed, leading to the key insight that, in addition to the HVAC system, the energy used by miscellaneous plug loads which include IT equipment must also be addressed.
Abstract: A holistic approach to reducing the energy footprint of large commercial buildings is proposed. A detailed energy use breakdown within a modern building is presented, leading to the key insight that, in addition to the HVAC system, the energy used by miscellaneous plug loads which include IT equipment must also be addressed. An actuation framework is proposed to control plug-loads and the HVAC system for energy savings.
138 citations
TL;DR: A specification methodology and design space exploration framework are proposed to raise the level of abstraction at which building control systems are designed, to reduce design effort, and to lower implementation cost.
Abstract: This article addresses the challenge of realizing the building automation and control system using a distributed network of embedded computers. A specification methodology and design space exploration framework are proposed to raise the level of abstraction at which building control systems are designed, to reduce design effort, and to lower implementation cost.
137 citations
TL;DR: Using on-chip monitors to significantly improve the sensitivity of side-channel signal analysis techniques to malicious inclusions in integrated circuits known as hardware Trojans is described.
Abstract: This paper describes using on-chip monitors to significantly improve the sensitivity of side-channel signal analysis techniques to malicious inclusions in integrated circuits known as hardware Trojans.
60 citations
TL;DR: A richer set of microarchitectural primitives is identified that allows us to describe complete systems by composition alone and enables us to build models faster and to avoid common modeling errors.
Abstract: Although communication fabrics at the microarchitectural level are mainly composed of standard primitives such as queues and arbiters, to get an executable model one has to connect these primitives with glue logic to complete the description. In this paper we identify a richer set of microarchitectural primitives that allows us to describe complete systems by composition alone. This enables us to build models faster (since models are now simply wiring diagrams at an appropriate level of abstraction) and to avoid common modeling errors such as inadvertent loss of data due to incorrect timing assumptions. Our models are formal and they are used for model checking as well as dynamic validation and performance modeling. However, unlike other formalisms this approach leads to a precise yet intuitive graphical notation for microarchitecture that captures timing and functionality in sufficient detail to be useful for reasoning about correctness and for communicating microarchitectural ideas to RTL and circuit designers and validators.
54 citations
TL;DR: This work focuses on significantly increasing the value of test data and the yield learning rate, which is a critical factor in the success of an IC in the market place.
Abstract: The yield of an integrated circuit (IC) is well known to be a critical factor in the success of an IC in the market place. Achieving high stable yields helps ensure that the product is profitable and meets quality and reliability objectives. When a new manufacturing process is introduced, or a new product is introduced on a mature manufacturing process, yields will tend to be significantly lower than acceptable. The ability to meet profitability and quality objectives, and perhaps more importantly, time-to-market and time-to-volume objectives depend greatly on the rate at which these low yields can be ramped up. While the yield ramp depends on both the yield learning and yield enhancement cycle times, this work focuses on significantly increasing the value of test data and the yield learning rate.
49 citations
TL;DR: In this article, an adaptive test scheme for analog circuits that capitalizes on alternate test to achieve a low cost for the majority of fabricated devices is presented, where the small fraction of devices for which the alternate test decision may be prone to error are identified and further action is taken.
Abstract: Adaptive test is a promising approach for test cost reduction. This article presents an adaptive test scheme for analog circuits that capitalizes on alternate test to achieve a low cost for the majority of fabricated devices. The small fraction of devices for which the alternate test decision may be prone to error are identified and further action is taken.
44 citations
TL;DR: This paper presents a simulation environment which allows for a visual design process ultimately leading to a formal model which can be efficiently simulated.
Abstract: The simulation of biological systems prior to their physical implementation can save time, money, and potentially provide insights into alternate designs. This paper presents a simulation environment which allows for a visual design process ultimately leading to a formal model which can be efficiently simulated.
39 citations
TL;DR: This article shows how abstracting these reactions appropriately provide a formalism to describe computation that is familiar to electrical engineers and computer scientists.
Abstract: Molecular reactions are a common occurrence in biological systems. These reactions are tremendously varied and can be extraordinarily complex. This article, however, shows how abstracting these reactions appropriately provide a formalism to describe computation that is familiar to electrical engineers and computer scientists.
38 citations
TL;DR: In this paper, the authors revisited the digitization journey of wireless systems and the motivations that have driven this research field, gave a brief yet concise summary of state-of-the-art solutions, and offers insights for future developments.
Abstract: In this review article, the author revisits the digitization journey of wireless systems and the motivations that have driven this research field, gives a brief yet concise summary of state-of-the-art solutions, and offers insights for future developments.
33 citations
TL;DR: A variety of yield-learning techniques are essential since no single approach can effectively find every manufacturing perturbation that can lead to yield loss.
Abstract: A variety of yield-learning techniques are essential since no single approach can effectively find every manufacturing perturbation that can lead to yield loss. Test structures, for example, can range from being simple in nature (combs and serpentine structures for measuring defect-density and size distributions) to more complex, active structures that include transistors, ring oscillators, and SRAMs. Test structures are designed to provide seamless access to a given failure type: its size, its location, and possibly other pertinent characteristics.
32 citations
TL;DR: A low-cost solution for hardware IP protection during evaluation is proposed, by embedding a hardware Trojan inside an IP in the form of a finite state machine that effectively puts an expiry date on the usage of the IP.
Abstract: The authors propose a low-cost solution for hardware IP protection during evaluation, by embedding a hardware Trojan inside an IP in the form of a finite state machine. The Trojan disrupts the normal functional behavior of the IP on occurrence of a sequence of rare events, thereby effectively putting an expiry date on the usage of the IP.
TL;DR: This article outlines bio-design automation using two complementary design approaches, bottom-up modular construction from biological primitives and pathway-based approaches, and highlights future challenges for both.
Abstract: Through principled engineering methods, synthetic biology aims to build specialized biological components that can be modularly composed to create complex systems. This article outlines bio-design automation using two complementary design approaches, bottom-up modular construction from biological primitives and pathway-based approaches. The article also highlights future challenges for both.
TL;DR: A design flow for BAC systems is proposed that enables integrating heterogeneous input models, conducts automatic design space exploration, and performs software synthesis on distributed platforms while guaranteeing correctness and reducing communication load.
Abstract: In this paper, we proposed a design flow for BAC systems that enables integrating heterogeneous input models, conducts automatic design space exploration, and performs software synthesis on distributed platforms while guaranteeing correctness and reducing communication load. We believe these capabilities can enable the building designers to better adopt model-based design methodologies, and facilitate them to improve design productivity, optimize system performance, and reduce cost.
TL;DR: This paper discusses the reuse and retargeting of test instruments and test patterns using the IEEE P1687 standard in an era where reuse of existing functional elements and integration of IP blocks is accelerating rapidly.
Abstract: This paper discusses the reuse and retargeting of test instruments and test patterns using the IEEE P1687 standard in an era where reuse of existing functional elements and integration of IP blocks is accelerating rapidly. It briefly discusses the deficiencies of existing 1149.1 (JTAG) and 1500 standards and demonstrates how the new standard, P1687, plugs these exposures by specifying JTAG as an off-chip to on-chip interface to the instrument access infrastructure. It provides a simple example to underscore the need for the standard and then builds on this example to show how the standard can be used for more complex situations.
TL;DR: The HEALICs program as mentioned in this paper enhances wireless systems with sensors, actuators, and mixed-signal control loops in order to improve their performance yield, which can be classified into two categories: sensor-based and actuator-based.
Abstract: This article discusses the goals and recent achievements of the HEALICs program. The program's aim is to enhance wireless systems with sensors, actuators, and mixed-signal control loops in order to improve their performance yield.
TL;DR: The role of a building information system in reducing building energy consumption as well as in providing demand response, is explored, and case studies of real use are presented.
Abstract: An energy information system that acquires and aggregates information from various sensors within buildings is presented. The role of a building information system in reducing building energy consumption as well as in providing demand response, is explored, and case studies of real use are presented.
TL;DR: The key contribution of this work lies in the ability to both determine the DUT specifications as well as the underlying Spice-level model parameters from the same DUT test response on a per chip basis, thereby providing quicker and higher diagnostic resolution.
Abstract: In this paper, an efficient methodology for die level test-and-diagnosis for Analog/RF circuits is developed. The key contribution of this work lies in the ability to both determine the DUT specifications as well as the underlying Spice-level model parameters from the same DUT test response on a per chip basis, thereby providing quicker and higher diagnostic resolution. The test and diagnosis procedures are enabled by a new computationally efficient test stimulus generation algorithm that simultaneously targets test sensitivity and parameter model diagnosability. This allows cause-effect analysis to be performed that relates perturbations in the spice-level model parameters to the DUT performance metrics (specifications). Further, cause-effect diagnosis is achieved at a test cost comparable to prior testing schemes that target only pass/ fail classification of tested devices.
TL;DR: An occupancy-driven HVAC control framework for more effective heating and cooling management and sensing and leveraging user context information is described.
Abstract: HVAC systems are eventually needed to maintain comfort for occupants, and as a result sensing and leveraging user context information is critical for the energy-efficient operation of buildings. This article describes an occupancy-driven HVAC control framework for more effective heating and cooling management.
TL;DR: The level of correlation of SLT failures to parameters from other testing steps is studied for an in-production IC in this work to evaluate if the system-level failures of an IC can be identified at otherTesting steps.
Abstract: This paper discusses our experience with the advantages of having SLT in an industrial test flow. In addition, the level of correlation of SLT failures to parameters from other testing steps is also studied for an in-production IC in this work to evaluate if the system-level failures of an IC can be identified at other testing steps. Note that the correlation study performed in this paper is not intended to determine whether the SLT failures can indeed be effectively identified using parameters measured at other testing steps, but rather only to evaluate the difficulty of finding a high level of correlation.
TL;DR: This paper presents a methodology to use global and local performance sensors, allowing the circuits to be optimized for power and/or performance.
Abstract: This paper presents a methodology to use global and local performance sensors, allowing the circuits to be optimized for power and/or performance.
TL;DR: A comprehensive methodology that addresses the prevention and identification of systematic defects and a fast and accurate defect simulation framework called SLIDER (Simulation of Layout-Injected Defects for Electrical Responses) has been developed.
Abstract: Design-induced systematic defects are serious threats to the semiconductor industry. This paper develops novel techniques to identify and prevent such defects, which facilitate to evaluate the effectiveness of DFM rules and improve the manufacturing process and design for yield enhancement.
TL;DR: A SAT-based ATPG flow for generating high quality test patterns while applicable to large industry designs is proposed.
Abstract: ATPG based on Boolean Satisfiability (SAT) could be a promising alternative to structural test generation algorithms. This article proposes a SAT-based ATPG flow for generating high quality test patterns while applicable to large industry designs.
TL;DR: This paper performs fault injection simulation to analyze the impact of intermittent faults, which is an important step towards the development of mitigation techniques for such threats.
Abstract: Intermittent faults, being serious concerns for deep-submicron integrated circuits, are not well studied in the literature. This paper performs fault injection simulation to analyze the impact of intermittent faults, which is an important step towards the development of mitigation techniques for such threats.
TL;DR: An alternative “power contributor”based approach to cell leakage characterization that exploits inherent separability of power consumption for different portions of a cell is described.
Abstract: Low-power or power-aware design is one of the greatest challenges facing the semiconductor industry. The fidelity of low power design is dependent on the accuracy of power modeling across a wide range of PVT values. This paper describes an alternative “power contributor”based approach to cell leakage characterization that exploits inherent separability of power consumption for different portions of a cell. An experimental use of this approach is also presented that demonstrates how the effort to characterize leakage power can be greatly reduced with only a marginal impact on accuracy.
TL;DR: A new algorithm is addressed with a significant speed-up of over 100x, while at the same time reduces test time by 48% and improves fault coverage by 15% in commercial mixed-signal designs.
Abstract: In this contribution, the authors describe an application of Defect Oriented Testing (DOT) to commercial mixed-signal designs. A major challenge of DOT application to these designs is the enormous simulation time typically required. The authors address this major challenge with a new algorithm that provides a significant speed-up of over 100x, while at the same time reduces test time by 48% and improves fault coverage by 15%.
TL;DR: The authors in this paper present a 45-nm on-chip aging sensor that directly monitors circuit performance degradation during dynamic operation.
Abstract: Asymmetric aging under different workload profiles requires on-chip aging sensors to be sensitive to signal edge degradation. The authors in this paper present a 45-nm on-chip aging sensor that directly monitors circuit performance degradation during dynamic operation.
TL;DR: In this paper, a self-healing 60 GHz transceiver architecture is proposed which employs information collected from on-chip sensors to intelligently adjust various tuning knobs and significantly improve the posthealing performance.
Abstract: This article discusses a self-healing 60-GHz transceiver architecture which employs information collected from on-chip sensors to intelligently adjust various tuning knobs and significantly improve the post-healing performance yield.
TL;DR: The new face of the well-known transistor stuck-open fault model in modern nanometer technologies is discussed and new detection methods that improve the robustness of tests are proposed.
Abstract: Failure analysis and fault modeling of integrated circuits have always been fields that require continuous revision and update as manufacturing processes evolve. This paper discusses the new face of the well-known transistor stuck-open fault model in modern nanometer technologies and proposes new detection methods that improve the robustness of tests.
TL;DR: Insight into the new features, changes and the reasons for the same of System Verilog Assertions standardization exposes users of SVA to the direction the standard is evolving.
Abstract: This paper provides insight into the development of System Verilog Assertions standardization efforts. Specifically it covers the evolution from Accellera 3.1a version to its current state of standardization (the upcoming SVA2012 release). Insight into the new features, changes and the reasons for the same exposes users of SVA to the direction the standard is evolving.
TL;DR: This paper presents the design space exploration of parallel embedded architectures that natively support Clifford algebra with different costs, performance and precision.
Abstract: Clifford (geometric) algebra is a natural and intuitive way to model geometric objects and their transformations. It has important applications in a variety of fields, including robotics, machine vision and computer graphics, where it has gained a growing interest. This paper presents the design space exploration of parallel embedded architectures that natively support Clifford algebra with different costs, performance and precision. Results show an effective 5x average speedup for Clifford products compared with a software library developed specifically for Clifford algebra.