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Proceedings ArticleDOI

26.6 A 6.5µW 10kHz-BW 80.4dB-SNDR Continuous-Time ΔΣ Modulator with G m -Input and 300mV pp Linear Input Range for Closed-Loop Neural Recording

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TLDR
A continuous-time delta-sigma modulator (CT-ALM) with Gm -input for closed-loop neural recording achieves a high input impedance, 300mVpp linear input range, 80.4dB SNDR, and 76dB CMRR, and consumes only 6.5μW with a signal bandwidth of 10kHz.
Abstract
Closed-loop neural recording requires a front-end with a wide DR to record small neural signals without distortion in the presence of a DC electrode offset (~50mV) and a large stimulation artifact (~ 200mV pp ). To remove DC offset, a conventional architecture uses an AC-coupled LNA and a subsequent ADC [1]. However, to realize a small HPF cut-off frequency ( 80dB), a large linear operating range (>250mV), a high DC input impedance (>1GΩ), and a large common-mode rejection (>70dB). Fulfilling all these requirements often leads to ADCs with poor energy-efficiency [2], [3]. This paper presents a continuous-time delta-sigma modulator (CT-ALM) with G m -input for closed-loop neural recording. It achieves a high input impedance, 300mV pp linear input range, 80.4dB SNDR, and 76dB CMRR, and consumes only 6.5μW with a signal bandwidth of 10kHz. This corresponds to a 172.3dB FOM.

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Journal ArticleDOI

A 6.5- μ W 10-kHz BW 80.4-dB SNDR G m -C-Based CT ∆∑ Modulator With a Feedback-Assisted G m Linearization for Artifact-Tolerant Neural Recording

TL;DR: The feedback-assisted G-sub m-based continuous-time delta–sigma modulator (CTDSM) is presented, which achieves a high input impedance, 300-mVpp linear input range, 80.4-dB signal-to-noise and distortion ratio (SNDR), 81-dB dynamic range (DR), and 76-dB common-mode rejection ratio (CMRR) and consumes only 6.5 kHz.
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A 112-dB SFDR 89-dB SNDR VCO-Based Sensor Front-End Enabled by Background-Calibrated Differential Pulse Code Modulation

TL;DR: Compared with conventional VCO-based quantizers, the proposed design leverages differential pulse-code modulation (DPCM) from compression theory to substantially reduce the amplitude of the signal incident to the VCO quantizer, thereby achieving an ultra-low total harmonic distortion (THD) of −112 dB.
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A 124 dB dynamic range sigma-delta modulator applied to non-invasive EEG acquisition using chopper-modulated input-scaling-down technique

TL;DR: A wide DR Σ∆ modulator with chopper-modulated input-scaling-down (CM-ISD) technique has been proposed to deal with large input set while extending dynamic range, showing its potential in advanced non-invasive BCI systems.
Proceedings ArticleDOI

Automated Distributed Element Model Generation for Neural Interface Co-Design

TL;DR: A scripted distributed element modeling framework is presented to enable process-portable co-design of neural recording and stimulation circuits and other applications that require co- design with an electrode-electrolyte interface, and it is shown that time-domain artifact cancellation techniques outperform frequency-domain techniques for concurrent neural recording
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A 0.0046-mm2 Two-Step Incremental Delta–Sigma Analog-to-Digital Converter Neuronal Recording Front End With 120-mVpp Offset Compensation

TL;DR: In this paper , the authors present a recording front end for high-density CMOS neuronal probes with in situ digitization and electrode offset voltage compensation, which is based on a continuous-time (CT) two-step (TS) incremental delta-sigma.
References
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Proceedings ArticleDOI

A 0.013mm 2 5μW DC-coupled neural signal acquisition IC with 0.5V supply

TL;DR: This work presents a neural interface in 65nm CMOS and operating at a 0.5V supply that obtains performance comparable or superior to state-of-the-art systems in a silicon area over 3× smaller by using a scalable architecture that avoids on-chip passives and takes advantage of high-density logic.
Journal ArticleDOI

A Continuous-Time Delta-Sigma Modulator Using a Modified Instrumentation Amplifier and Current Reuse DAC for Neural Recording

TL;DR: The modification of an IA for operation as an integrator in a delta-sigma modulator and the current reuse of the feedback DAC current to bias this integrator stage are proposed and the total power consumption of the modulator is reduced by 22%.
Proceedings ArticleDOI

A 0.025-mm 2 0.8-V 78.5dB-SNDR VCO-Based Sensor Readout Circuit in a Hybrid PLL-ΔΣM Structure

TL;DR: A capacitive-coupled VCO-based sensor readout featuring a hybrid PLL-Sigma structure that leverages phase-locking and PFD array to concurrently perform quantization and DEM and a low-cost in-cell DWA scheme is presented to enable highly linear tri-level DAC.
Proceedings ArticleDOI

A 15.2-ENOB continuous-time ΔΣ ADC for a 200mV pp -linear-input-range neural recording front-end

TL;DR: A 15.2b-ENOB CT ΔΣΜ with 187dB FOM is presented, which along with an 8x-gain capacitively coupled chopper instrumentation amplifier (CCIA), realizes a front-end that can digitize neural signals from 1Hz to 5kHz in the presence of 200mV artifacts.
Proceedings ArticleDOI

A 3.9μW, 81.3dB SNDR, DC-coupled, Time-based Neural Recording IC with Degeneration R-DAC for Bidirectional Neural Interface in 180nm CMOS

TL;DR: A 5-bit VCO-based neural recording IC is presented, which directly quantizes the input signal and achieves a large dynamic range (DR) to process the small-amplitude neural signal in the presence of the large-AMplitude stimulation artifact.
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