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Proceedings ArticleDOI

3DLAT: TSV-based 3D ICs crosstalk minimization utilizing Less Adjacent Transition code

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TLDR
A novel ω-LAT coding scheme is proposed to reduce the capacitive crosstalk and minimize the power consumption overhead in the TSV array and combining with the Transition Signaling, the LAT coding scheme restricts the number of transitions in every transmission cycle to minimize the crosStalk and power consumption.
Abstract
3D integration is one of the promising solutions to overcome the interconnect bottleneck with vertical interconnect through-silicon vias (TSVs). This paper investigates the crosstalk in 3D IC designs, especially the capacitive crosstalk in TSV interconnects. We propose a novel ω-LAT coding scheme to reduce the capacitive crosstalk and minimize the power consumption overhead in the TSV array. Combining with the Transition Signaling, the LAT coding scheme restricts the number of transitions in every transmission cycle to minimize the crosstalk and power consumption. Compared to other 3D crosstalk minimization coding schemes, the proposed coding can provide the same delay reduction with more affordable overhead. The performance and power analysis show that when ω is 4, the proposed LAT coding scheme can achieve 38% interconnect crosstalk delay reduction compared to the data transmission without coding. By reducing the value of ω, further reduction can be achieved1.

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Citations
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Journal ArticleDOI

An Enhancement of Crosstalk Avoidance Code Based on Fibonacci Numeral System for Through Silicon Vias

TL;DR: An enhanced code based on the Fibonacci number system (FNS) to suppress the crosstalk noise below 6C level is proposed, in which both the redundancy of numbers and the nonuniqueness of fibonacci-based binary codeword are utilized to search the proper codewords.
Journal ArticleDOI

Time-division-multiplexing–wavelength- division-multiplexing-based architecture for ONoC

TL;DR: The simulation results show that TDM–WDM-based ONoC has better performance compared with equivalent OCS-mesh O noC under a uniform traffic pattern and the real science application based on the PARSEC benchmark.
Journal ArticleDOI

High-Level Energy Estimation for Submicrometric TSV Arrays

TL;DR: This model is the first high-level model including the effects of the voltage-dependent metal–oxide–semiconductor (MOS) capacitances surrounding each TSV and a possible temporal misalignment between the input signals and reveals a possibility to easily boost the efficiency of existing low-power codes for TSV structures by over 10% without affecting the coding efficiency for the planar metal wires or the encoder complexity.
Journal ArticleDOI

A Survey on the Security of Wired, Wireless, and 3D Network-on-Chips

TL;DR: In this paper, the authors review security threats and countermeasures proposed so far for wired NoCs, wireless NoC, and 3D NoC and aim at giving the readers an insight into the attacks and weaknesses/strengths of countermeasures.
Journal ArticleDOI

Edge effects on the TSV array capacitances and their performance influence

TL;DR: The experimental results show that for 48 different modern TSV structures, the presented model reduces the root-mean-square-error (RMSE) by over 95%, compared to the previously used model, which proves that existing TSV coding approaches, derived by means of the previous model, are impractical due to the edge effects.
References
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Journal ArticleDOI

Bus-invert coding for low-power I/O

TL;DR: In this article, the bus-invert method of coding the I/O was proposed to decrease the bus activity and thus decrease the peak power dissipation by 50% and the average power disipation by up to 25%.

Bus-invert coding for low-powerI/O

M.R. Stan
TL;DR: The bus-invert method of coding the I/O is proposed which lowers the bus activity and thus decreases theI/O peak power dissipation by 50% and the I-O average power Dissipation by up to 25%.
Journal ArticleDOI

Reliability challenges in 3D IC packaging technology

TL;DR: This paper presents a projection of the reliability challenges in 3D IC packaging technology on the basis of what the authors have known from flip chip technology.
Book

Three-Dimensional Integrated Circuit Design

TL;DR: In this article, the first book on 3D integrated circuit design, covering all of the technological and design aspects of this emerging design paradigm, while proposing effective solutions to specific challenging problems concerning the design of three-dimensional integrated circuits.
Proceedings ArticleDOI

Bus encoding to prevent crosstalk delay

TL;DR: This paper finds that a 32-bit bus can be encoded with 40 wires using a code with memory or 46 wires with a memoryless code, in comparison to the 63 wires required with simple shielding.
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