Journal ArticleDOI
A 10-MHz 85.1-dB SFDR 1.1-mW continuous-time Delta-sigma modulator employing calibration-free SC DAC and passive front-end low-pass filter
Wei Jin,Kong-Pang Pun +1 more
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TLDR
In this paper , the authors demonstrate the circuit technique of a highly power-efficient continuous-time (CT) Delta-sigma modulator (DSM) based on a switched-capacitor (SC) feedback digital-to-analog converter (DAC) and a passive front-end low-pass filter (LPF).About:
This article is published in Microelectronics Journal.The article was published on 2022-12-01. It has received 1 citations till now. The article focuses on the topics: Computer science & Spurious-free dynamic range.read more
Citations
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Journal ArticleDOI
A 1.3-mW 73.3-dB DR 10-MHz Bandwidth CT Delta-Sigma Modulator with a Charge-Recycled SC DAC and 52.7-dB Alias Rejection
TL;DR: In this article , an intrinsically highly linear 5-level switched-capacitor DAC with a power-saving charge recycling technique for wideband continuous-time (CT) Delta-Sigma modulators (DSMs) is presented.
References
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Journal ArticleDOI
A continuous-time /spl Sigma//spl Delta/ Modulator with reduced sensitivity to clock jitter through SCR feedback
TL;DR: This paper presents a means to overcome the high sensitivity of continuous-time sigma-delta (/spl Sigma//spl Delta/) modulators to clock jitter by using a modified switched-capacitor structure with resistive element in the continuous- time feedback digital-analog converter (DAC).
Journal ArticleDOI
A 0.5-V 74-dB SNDR 25-kHz Continuous-Time Delta-Sigma Modulator With a Return-to-Open DAC
TL;DR: A 0.5-V third-order one-bit fully-differential continuous-time DeltaSigma modulator is presented, which uses true low-voltage design techniques, and does not require internal voltage boosting or low-threshold devices.
Journal ArticleDOI
Exact Analysis of Linear Circuits Containing Periodically Operated Switches with Applications
TL;DR: An exact analysis of linear circuits containing periodically operated switches with exponentially modulated cisoidal inputs using the state-space approach is presented and explicit closed form solutions for both the time and frequency domain suitable for digital computation are obtained.
Journal ArticleDOI
A 0.039 mm $^2$ Inverter-Based 1.82 mW 68.6 $~$ dB-SNDR 10 MHz-BW CT- $\Sigma\Delta$ -ADC in 65 nm CMOS Using Power- and Area-Efficient Design Techniques
TL;DR: This work presents design techniques for the realization of compact, low-power CT- ΣΔ-ADCs in ultra-deep-submicron CMOS, a resonant single-opamp third-order integrator with loss compensation, and an inverter-based opamp with digitally assisted biasing and common mode control.
Journal ArticleDOI
A 0.029-mm 2 17-fJ/Conversion-Step Third-Order CT $\Delta\Sigma$ ADC With a Single OTA and Second-Order Noise-Shaping SAR Quantizer
TL;DR: This paper presents a compact and power efficient third-order continuous-time (CT) delta-sigma analog-to-digital converter (ADC) with a single operational transconductance amplifier (OTA).
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