Journal ArticleDOI
A 90-dB SNR 2.5-MHz output-rate ADC using cascaded multibit delta-sigma modulation at 8/spl times/ oversampling ratio
Ichiro Fujimori,Lorenzo Longo,Armond Hairapetian,K. Seiyama,Steve Kosic,Jun Cao,Shu-lap Chan +6 more
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TLDR
A 16-b 2.5-MHz output-rate analog-to-digital converter for wireline communications and high-speed instrumentation has been developed with 2-1-1 cascaded delta-sigma modulator employing 4-b quantizers in every stage to increase the spurious-free dynamic-range (SFDR).Abstract:Â
A 16-b 2.5-MHz output-rate analog-to-digital converter (ADC) for wireline communications and high-speed instrumentation has been developed. A 2-1-1 cascaded delta-sigma modulator (DSM) employing 4-b quantizers in every stage makes all quantization noise sources negligible at 8/spl times/ oversampling ratio, Data weighted averaging with bi-directional rotation eliminates tones generated by multibit digital-to-analog converter (DAC) nonlinearity to increase the spurious-free dynamic-range (SFDR). Switched-capacitor design techniques using low-threshold transistors reduce front-end sampling distortion. The 24.8 mm/sup 2/ chip in 0.5-/spl mu/m CMOS also integrates the decimation filter and voltage reference. The ADC achieves 90-dB signal-to-noise ratio (SNR) in the 1.25-MHz bandwidth and 102-dB SFDR with 270-mW power dissipation.read more
Citations
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Patent
Fibre channel arbitrated loop bufferless switch circuitry to increase bandwidth without significant increase in cost
Alistair D. Black,Kurt Chan +1 more
TL;DR: In this article, a switch, switched architecture and process for transferring data through an FCAL switch is disclosed, which uses multiple switch control circuits each coupled to one FCAL network and all connected to a crossbar switch.
Journal ArticleDOI
A continuous-time sigma-delta modulator with 88-dB dynamic range and 1.1-MHz signal bandwidth
TL;DR: In this paper, a third-order continuous-time /spl Sigma/spl Delta/ modulator with 5-bit internal quantization was realized in a 0.5-/spl mu/m double-poly triple-metal CMOS technology, with a chip area of 2.4 mm/sup 2/.
Journal ArticleDOI
A 70-mW 300-MHz CMOS continuous-time /spl Sigma//spl Delta/ ADC with 15-MHz bandwidth and 11 bits of resolution
Susana Paton,A. Di Giandomenico,Luis Hernandez,Andreas Wiesbauer,Thomas Pötscher,Martin Clara +5 more
TL;DR: A wide-bandwidth continuous-time sigma-delta ADC is implemented in a 0.13-/spl mu/m CMOS circuit that achieves a dynamic range of 11 bits over a bandwidth of 15 MHz.
Journal ArticleDOI
A cascaded continuous-time /spl Sigma//spl Delta/ Modulator with 67-dB dynamic range in 10-MHz bandwidth
TL;DR: In this article, a 2-2 cascaded continuous-time sigma-delta modulator is proposed, which consists of two stages with second-order continuous time resonator loopfilters, 4-bit quantizers, and feedback digital-to-analog converters.
Journal ArticleDOI
A 2.5-V sigma-delta modulator for broadband communications applications
TL;DR: This paper explores how oversampling and feedback can be employed in high-resolution /spl Sigma//spl Delta/ modulators to extend the signal bandwidth into the range of several megahertz when the oversampled ratio is constrained by technology limitations.
References
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Journal ArticleDOI
Linearity enhancement of multibit /spl Delta//spl Sigma/ A/D and D/A converters using data weighted averaging
R.T. Baird,Terri S. Fiez +1 more
TL;DR: A dynamic element matching algorithm, data weighted averaging, is introduced for use in multibit /spl Delta//spl Sigma/ data converters, resulting in a dynamic range improvement of 9 dB/octave when DAC errors dominate.
Journal ArticleDOI
Analog MOS integrated circuits for signal processing
TL;DR: That's it, a book to wait for in this month; even you have wanted for long time for releasing this book analog mos integrated circuits for signal processing; you may not be able to get in some stress, but now, the authors are coming to give you excellent solution.
Journal ArticleDOI
Addressing substrate coupling in mixed-mode ICs: simulation and power distribution synthesis
TL;DR: In this article, the authors describe new techniques for the simulation and power distribution synthesis of mixed analog/digital integrated circuits considering the parasitic coupling of noise through the common substrate by spatially discretizing a simplified form of Maxwell's equations, a three-dimensional linear mesh model of the substrate is developed.
Journal ArticleDOI
A cascaded sigma-delta pipeline A/D converter with 1.25 MHz signal bandwidth and 89 dB SNR
TL;DR: A low-noise multibit sigma-delta analog-to-digital converter (ADC) architecture suitable for operation at low oversampling ratios is presented, using an efficient high-resolution pipelined quantizer while avoiding loop stability degradation caused by pipeline latency.
Journal ArticleDOI
Noise-shaped multbit D/A convertor employing unit elements
Richard Schreier,B. Zhang +1 more
TL;DR: Simulations indicate that first-order, second-order and bandpass noise-shaping are all possible in the technique that enables the use of multibit feedback in delta-sigma A/D and D/A convertors.
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Linearity enhancement of multibit /spl Delta//spl Sigma/ A/D and D/A converters using data weighted averaging
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