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Open AccessProceedings ArticleDOI

A datapath synthesis system for the reconfigurable datapath architecture

TLDR
A datapath synthesis system (DPSS) for the reconfigurabledatapath architecture (rDPA) that allows automatic mapping of high level descriptions onto the rDPA without manual interaction is presented.
Abstract
A datapath synthesis system (DPSS) for the reconfigurable datapath architecture (rDPA) is presented. The DPSS allows automatic mapping of high level descriptions onto the rDPA without manual interaction. The required algorithms of this synthesis system are described in detail. Optimization techniques like loop folding or loop unrolling are sketched. The rDPA is scalable to arbitrarily large arrays and reconfigurable to be adaptable to the computational problem. Fine grained parallelism is achieved by using simple reconfigurable processing elements which are called datapath units (DPUs). The rDPA can be used as a reconfigurable ALU for bus oriented systems as well as for rapid prototyping of high speed datapaths.

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Citations
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Proceedings ArticleDOI

A decade of reconfigurable computing: a visionary retrospective

TL;DR: The paper surveys a decade of R&D on coarse grain reconfigurable hardware and related CAD, points out why this emerging discipline is heading toward a dichotomy of computing science, and advocates the introduction of a new soft machine paradigm to replace CAD by compilation.
Proceedings ArticleDOI

Exploiting Loop-Level Parallelism on Coarse-Grained Reconfigurable Architectures Using Modulo Scheduling

TL;DR: A modulo scheduling algorithm to exploit loop-level parallelism for coarse-grained reconfigurable architectures and is a key part of theDRESC Dynamically Reconfigurable Embedded Systems Compiler.
Patent

Reconfigurable computing architecture for providing pipelined data paths

TL;DR: In this article, the authors propose a reconfigurable data path that combines static and dynamic control information to reduce the amount of dynamic control used to achieve flexible operation by using a combination of dynamic and static control information.
Proceedings ArticleDOI

Coarse grain reconfigurable architectures

TL;DR: The paper gives a brief survey over a decade of R&D on coarse grain reconfigured hardware and related compilation techniques and points out its significance to the emerging discipline of reconfigurable computing.
References
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Book

Synthesis and optimization of digital circuits

TL;DR: This book covers techniques for synthesis and optimization of digital circuits at the architectural and logic levels, i.e., the generation of performance-and-or area-optimal circuits representations from models in hardware description languages.
Book

High ― Level Synthesis: Introduction to Chip and System Design

TL;DR: This paper presents a methodology for High-Level Synthesis of Architectural Models in Synthesis and its applications in Design Description Languages and Design Representation and Transformations.
Journal ArticleDOI

A novel ASIC design approach based on a new machine paradigm

TL;DR: In this paper, a design methodology for rapid implementation of cheap high-performance ASICs (application-specific integrated circuits) is introduced, based on a novel sequential machine paradigm where execution is used (being orders of magnitude more efficient) instead of simulation and where programmers may do the design job, rather than real hardware designers.
Proceedings ArticleDOI

A data-parallel programming model for reconfigurable architectures

TL;DR: A vector based data-parallel model and its mapping to a reconfigurable architecture are introduced, including parallel prefix or scan operators and the language supporting this model is a subset of the C programming language.
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