Proceedings ArticleDOI
A novel synthesis approach for active leakage power reduction using dynamic supply gating
Swarup Bhunia,Nilanjan Banerjee,Qikai Chen,Hamid Mahmoodi,Kaushik Roy +4 more
- pp 479-484
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TLDR
A logic synthesis approach based on Shannon expansion is proposed that dynamically applies supply gating to idle parts of general logic circuits even when they are performing useful computation.Abstract:
Due to exponential increase in subthreshold leakage with technology scaling and temperature increase, leakage power is becoming a major fraction of total power in the active mode. We present a novel low-cost design methodology with associated synthesis flow for reducing both switching and active leakage power using dynamic supply gating. A logic synthesis approach based on Shannon expansion is proposed that dynamically applies supply gating to idle parts of general logic circuits even when they are performing useful computation. Experimental results on a set of MCNC benchmark circuits in a predictive 70nm process exhibits improvements of 15% to 88% in total active power compared to the results obtained by a conventional optimization flow.read more
Citations
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CRISTA: A New Paradigm for Low-Power, Variation-Tolerant, and Adaptive Circuit Synthesis Using Critical Path Isolation
TL;DR: A novel paradigm for low-power variation-tolerant circuit design called critical path isolation for timing adaptiveness (CRISTA), which allows aggressive voltage scaling and isolate and predict the set of possible paths that may become critical under process variations.
Journal ArticleDOI
Power gating: Circuits, design methodologies, and best practice for standard-cell VLSI designs
TL;DR: Power gating has become one of the most widely used circuit design techniques for reducing leakage current as discussed by the authors, but its application to standard-cell VLSI designs involves many careful considerations.
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A CMOS Thermal Sensor and Its Applications in Temperature Adaptive Design
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On Process Variation Tolerant Low Cost Thermal Sensor Design
TL;DR: A process variation tolerant thermal sensor design with (i) active compensation circuitry and (ii) signal dithering based self calibration technique to meet the above requirements in 32nm technology is presented.
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Hybrid CMOS-STTRAM non-volatile FPGA: design challenges and optimization approaches
TL;DR: A novel CMOS-STTRAM hybrid FPGA framework is proposed; the key design challenges are identified; and optimization techniques at circuit, architecture and application mapping levels are proposed.
References
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