A scheduling model for reduced CPU energy
F. Frances Yao,Alan J. Demers,Scott Shenker +2 more
- pp 374-382
TLDR
This paper proposes a simple model of job scheduling aimed at capturing some key aspects of energy minimization, and gives an off-line algorithm that computes, for any set of jobs, a minimum-energy schedule.Abstract:
The energy usage of computer systems is becoming an important consideration, especially for battery-operated systems. Various methods for reducing energy consumption have been investigated, both at the circuit level and at the operating systems level. In this paper, we propose a simple model of job scheduling aimed at capturing some key aspects of energy minimization. In this model, each job is to be executed between its arrival time and deadline by a single processor with variable speed, under the assumption that energy usage per unit time, P, is a convex function, of the processor speed s. We give an off-line algorithm that computes, for any set of jobs, a minimum-energy schedule. We then consider some on-line algorithms and their competitive performance for the power function P(s)=s/sup p/ where p/spl ges/2. It is shown that one natural heuristic, called the Average Rate heuristic, uses at most a constant times the minimum energy required. The analysis involves bounding the largest eigenvalue in matrices of a special type.read more
Citations
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Journal ArticleDOI
Energy-efficient algorithms for flow time minimization
Susanne Albers,Hiroshi Fujiwara +1 more
TL;DR: In this paper, the authors proposed a deterministic constant competitive online algorithm to schedule a sequence of jobs on a variable-speed processor so as to minimize the total cost consisting of the energy consumption and the total flow time of all jobs.
Proceedings ArticleDOI
Profile-Based Dynamic Voltage Scheduling Using Program Checkpoints
Ana Azevedo,Ilya Issenin,R. Cornea,Rajesh Gupta,Nikil Dutt,Alexander V. Veidenbaum,Alexandru Nicolau +6 more
TL;DR: This paper introduces a novel intra-task DVS technique under compiler control using program checkpoints, which handles multiple intra- task performance deadlines and modulates power consumption according to a run-time power budget.
Journal ArticleDOI
State-of-the-art research study for green cloud computing
TL;DR: This paper study state-of-the-art techniques and research related to power saving in the IaaS of a cloud computing system, which consumes a huge part of total energy in a cloud Computing system.
Journal ArticleDOI
GreenDCN: A General Framework for Achieving Energy Efficiency in Data Center Networks
Lin Wang,Fa Zhang,Jordi Arjona Aroca,Athanasios V. Vasilakos,Kai Zheng,Chenying Hou,Dan Li,Zhiyong Liu +7 more
TL;DR: A new framework is proposed to embrace the new opportunities brought by combining some special features of data centers with traffic engineering, and it is confirmed that, by using this framework, one can achieve up to 50 percent energy savings.
Journal ArticleDOI
The interplay of power management and fault recovery in real-time systems
TL;DR: The results show that traditional periodic checkpointing is not the best policy for the combined purpose of conserving energy and guaranteeing recovery, and better energy savings are possible through a nonuniform distribution of checkpoints that takes into account the energy consumption and reliability factors.
References
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Journal ArticleDOI
Scheduling Algorithms for Multiprogramming in a Hard-Real-Time Environment
C. L. Liu,James W. Layland +1 more
TL;DR: The problem of multiprogram scheduling on a single processor is studied from the viewpoint of the characteristics peculiar to the program functions that need guaranteed service and it is shown that an optimum fixed priority scheduler possesses an upper bound to processor utilization.
Journal ArticleDOI
Low-power CMOS digital design
TL;DR: In this paper, techniques for low power operation are presented which use the lowest possible supply voltage coupled with architectural, logic style, circuit, and technology optimizations to reduce power consumption in CMOS digital circuits while maintaining computational throughput.
Journal Article
Low-Power CMOS Digital Design
TL;DR: An architecturally based scaling strategy is presented which indicates that the optimum voltage is much lower than that determined by other scaling considerations, and is achieved by trading increased silicon area for reduced power consumption.
Proceedings ArticleDOI
Scheduling for reduced CPU energy
TL;DR: A new metric for cpu energy performance, millions-of-instructions-per-joule (MIPJ), and several methods for varying the clock speed dynamically under control of the operating system, and examine the performance of these methods against workstation traces.
Proceedings ArticleDOI
Comparing algorithm for dynamic speed-setting of a low-power CPU
TL;DR: This work clarifies a fundamental power vs. delay tradeoff, as well as the role of prediction and of smoothing in dynamic speed-setting policies, and concludes that success seemingly depends more on simple smoothing algorithms than on sophisticated prediction techniques.
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