Proceedings ArticleDOI
Adaptive test clock scheme for low transition LFSR and external scan based testing
S. Sivanantham,G. Gopakumar,A. Pandey,M. J. Paikada +3 more
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TLDR
This paper presents an approach to reduce the test time of an external test applied from an automatic test equipment by speeding up low activity cycles, keeping the power under control.Abstract:
This paper presents an approach to reduce the test time of an external test applied from an automatic test equipment by speeding up low activity cycles, keeping the power under control. Based on the signal transitions, which are used to control the power consumption of the Circuit under test, the clock frequency can be varied. Two different methods have been considered for controlling the scan clock frequency: using hardware control and using pre-simulated and stored test data where a dynamically controlled scan clock is used.read more
Citations
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Proceedings ArticleDOI
Adaptive Low Power RTPG for BIST based test applications
TL;DR: A Low Power Random Test Pattern Generator (LPRTPG) is presenting to improve the tradeoff between shift power reduction and the test coverage loss and to get the required tradeoff, an adaptive type technique is utilizing.
Journal Article
Design of low power Linear feedback shift register
TL;DR: The research showed that, pass transistor has smallest power consumption which is 3.1049 nano watts and required smallest number of transistor and layout area, which is 74 and 1137.76 micro square meter respectively.
System-On-a-Chip Test Data Compression and Decompression with Reconfigurable Serial Multiplier
S. Sivanantham,M. Padmavathy +1 more
TL;DR: A test data compression and decompression scheme using reconfigurable multipliers that reduces significant hardware by exploiting the advantage of using the existing circuitry in the circuit under test for decompression and improves encoding efficiency.
Journal Article
Built-in Self-Test Methodology for System-on-a-Chip Testing
S. Sivanantham,T Tresa +1 more
TL;DR: A test pattern generation methodology for detection of transition faults using in-circuit arithmetic circuits for reduced area overhead and the power of the test pattern generator is presented.
Journal ArticleDOI
Test Data Compression with Alternating Equal-Run-Length Coding
TL;DR: A new X-filling algorithm for test power reduction and a novel encoding technique for test data compression in scan-based VLSI testing and efficient decompression architecture is presented to decode the original data with lesser area overhead and power.
References
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Journal ArticleDOI
A tutorial on built-in self-test. I. Principles
TL;DR: An overview of built-in self-test (BIST) principles and practices is presented, and Linear feedback shift register theory is reviewed.
Proceedings ArticleDOI
DS-LFSR: a new BIST TPG for low heat dissipation
TL;DR: A test pattern generator for built-in self-test (BIST), which can reduce heat dissipation during test application, is proposed, and dual-speed LFSRs are designed to provide 13% to 70% reduction in the numbers of transitions with no loss of fault coverage and at very slight area overheads.
Proceedings ArticleDOI
Low power BIST via non-linear hybrid cellular automata
TL;DR: This paper proposes an algorithm to design a test pattern generator based on cellular automata for testing combinational circuits that effectively reduces power consumption while attaining high fault coverage and experimental results show that this approach reduces the power consumed during test by 34% on average.
Journal ArticleDOI
Test Data Compression Using Efficient Bitmask and Dictionary Selection Methods
Kanad Basu,Prabhat Mishra +1 more
TL;DR: A novel test data compression technique using bitmasks which provides a substantial improvement in the compression efficiency without introducing any additional decompression penalty is proposed.
Proceedings ArticleDOI
Low Transition LFSR for BIST-Based Applications
TL;DR: This paper presents a low transition test pattern generator, called LT-LFSR, to reduce average and peak power of a circuit during test by reducing the transitions within randomtest pattern and between consecutive patterns.