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Proceedings ArticleDOI

Advanced SOI substrate manufacturing

TLDR
In this article, the lattice mismatch between silicon and SiGe alloys, combined with layer transfer through the Smart Cut/spl trade/ technology, allow forming two types of strained Si -strained Si on SiGe on insulator, known as SGOI, and strained Si directly on the SiGe directly on a sSOI.
Abstract
300 mm SOI wafers with sub-100nm thick active Si layers are currently produced in large quantities and used in advanced microprocessor circuits. To further enhance the performance of the next generation of devices, strained Si layers on insulator are being developed. The lattice mismatch between silicon and SiGe alloys, combined with layer transfer through the Smart Cut/spl trade/ technology allow forming two types of strained Si - strained Si on SiGe on insulator, known as SGOI, and strained Si directly on insulator, known as sSOI. Fabrication methods and wafer characteristics for SOI, SGOI, and sSOI are discussed here.

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Citations
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Patent

Reverse construction memory cell

TL;DR: In this paper, a method of fabricating a memory cell comprises forming a plurality of doped semiconductor layers on a carrier substrate, and then depositing an insulating material into the plurality of trenches.
Patent

Silicon-on-plastic semiconductor device with interfacial adhesion layer

TL;DR: In this article, a semiconductor device with a polymer substrate and an interfacial adhesion layer over the polymer substrate is described, and methods for manufacturing the same are described. But the authors do not discuss the fabrication process.
Proceedings ArticleDOI

Sub-1V, Robust and Compact 6T SRAM cell in Double Gate MOS technology

TL;DR: The presented SRAM cell is a six transistors cell characterized by two word lines connected to the front and back gate of each access transistors, respectively, which shows excellent read/write cell stability at minimal transistor dimension.
Patent

Encapsulated dies with enhanced thermal performance

TL;DR: In this article, a plurality of flip-chip dies are attached on a top surface of a carrier, and a first mold compound is applied over the top of the carrier to encapsulate the plurality of flips.
Patent

Method for manufacturing an integrated circuit package

TL;DR: In this paper, a printed circuit board is provided with semiconductor die, which includes a back-end-of-line (BEOL) region, a Front-End-Of-Line (FEOL), and a semiconductor handle such that the BEOL region, the FEOL region and the handle are stacked.
References
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Journal ArticleDOI

Silicon on insulator material technology

M. Bruel
- 06 Jul 1995 - 
TL;DR: In this article, a silicon on insulator material technology based on wafer bonding is described, in which a heat treatment induces an in-depth microslicing of one of the two bonded wafers previously implanted with hydrogen.
Journal ArticleDOI

Frontiers of silicon-on-insulator

TL;DR: In this article, the authors discuss methods of forming silicon-on-insulator (SOI) wafers, their physical properties, and the latest improvements in controlling the structure parameters.
Journal ArticleDOI

The generic nature of SmartCut process for thin film transfer

TL;DR: In this paper, a specific case of thermally-induced splitting is investigated, where the splitting kinetics are controlled by hydrogen diffusion. And the latest results concerning new structures are presented.
Proceedings ArticleDOI

Preparation of novel SiGe-free strained Si on insulator substrates

TL;DR: A novel SiGe-free SSOI substrate technology has been described, which enables the fabrication of well controlled, epitaxially-defined, thin strained Si layers directly on insulator layers.
Book ChapterDOI

Smart Cut®: the technology used forhigh volume SOI wafer production

TL;DR: The Smart Cut® process is a breakthrough in material engineering, offering new material and structures to the industry where enabling materials are in high demand as mentioned in this paper, and is linked to cavity growth by an Ostwald ripening mechanism and crack propagation.
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