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Book ChapterDOI

An Efficient Algorithm for Reducing Wire Length in Three-Layer Channel Routing

01 Jan 2015-pp 145-156

TL;DR: An efficient polynomial time graph-based heuristic algorithm that minimizes the total wire length for most of the benchmark channel instances available in the reserved three-layer no-dogleg Manhattan channel routing model is developed.

AbstractIn VLSI physical design automation, channel routing problem (CRP) for minimizing total wire length to interconnect the nets of different circuit blocks is one of the most challenging requirements to enhance the performance of a chip to be designed. Interconnection with minimum wire length occupies minimum area and has minimum overall capacitance and resistance present in a circuit. Reducing the total wire length for interconnection minimizes the cost of physical wire segments required, signal propagation delays, electrical hazards, power consumption, the chip environment temperature, the heat of the neighboring interconnects or transistors, and the thermal conductivity of the surrounding materials. Thus, it meets the needs of green computing and has a direct impact on daily life and environment. Since the problem of computing minimum wire length routing solutions for three-layer no-dogleg general channel instance is NP-hard, it is interesting to develop heuristic algorithms that compute reduced total wire length routing solutions within practical time limit. In this paper, we have developed an efficient polynomial time graph-based heuristic algorithm that minimizes the total wire length for most of the benchmark channel instances available in the reserved three-layer no-dogleg Manhattan channel routing model. The results we compute are highly encouraging in terms of efficiency and performance of our algorithm in comparison to other existing algorithms for computing the same.

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Citations
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Journal ArticleDOI
TL;DR: The proposed method works efficiently for complex problems arise in VLSI physical design automation and it gives acceptable results in terms of different channel instances.
Abstract: Objectives: The wire length minimization of Channel routing problem is NP-hard. There are several heuristic algorithms available in the literature to get the feasible routing solutions using some limited instances. Here we want to generate all possible random channel instances based on Genetic Algorithm (GA). Methods/ Statistical Analysis: The present paper is described in three phases. In the first phase, we generate fixed size initial population based on some strategies and define the fitness value of each individual by the total number of vertical and horizontal constraints present in the channel. The best individual is obtained among the population based on height fitness value. In the second phase, we select two individuals based on Roulette Wheel Selection strategies and get two offspring's using single point crossover. We continue this process until the number of offspring's reached to the size of the population. To keep the population size fixed we apply reduction methods among the initial population along with all offspring are based on minimum fitness value. In the third phase, we randomly choose some channels for mutation and we find the best individuals among current population. This methodology will be continuing until and unless we reach the goal. Findings: The proposed method works efficiently for complex problems arise in VLSI physical design automation and it gives acceptable results in terms of different channel instances. Applications/Improvement: The newly designed method for different difficult channel instances generation techniques will help to judge any newly developed algorithm in the field of VLSI physical design automation.

References
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Book
01 Jan 1980
TL;DR: This new Annals edition continues to convey the message that intersection graph models are a necessary and important tool for solving real-world problems and remains a stepping stone from which the reader may embark on one of many fascinating research trails.
Abstract: Algorithmic Graph Theory and Perfect Graphs, first published in 1980, has become the classic introduction to the field. This new Annals edition continues to convey the message that intersection graph models are a necessary and important tool for solving real-world problems. It remains a stepping stone from which the reader may embark on one of many fascinating research trails. The past twenty years have been an amazingly fruitful period of research in algorithmic graph theory and structured families of graphs. Especially important have been the theory and applications of new intersection graph models such as generalizations of permutation graphs and interval graphs. These have lead to new families of perfect graphs and many algorithmic results. These are surveyed in the new Epilogue chapter in this second edition. New edition of the "Classic" book on the topic Wonderful introduction to a rich research area Leading author in the field of algorithmic graph theory Beautifully written for the new mathematician or computer scientist Comprehensive treatment

4,086 citations

Proceedings ArticleDOI
28 Jun 1971
TL;DR: The purpose of this paper is to introduce a new wire routing method for two layer printed circuit boards based on the newly developed channel assignment algorithm and requires many via holes.
Abstract: The purpose of this paper is to introduce a new wire routing method for two layer printed circuit boards. This technique has been developed at the University of Illinois Center for Advanced Computation and has been programmed in ALGOL for a B5500 computer. The routing method is based on the newly developed channel assignment algorithm and requires many via holes. The primary goals of the method are short execution time and high wireability. Actual design specifications for ILLIAC IV Control Unit boards have been used to test the feasibility of the routing technique. Tests have shown that this algorithm is very fast and can handle large boards.

650 citations

Journal ArticleDOI
TL;DR: Two new algorithms merge nets instead of assigning horizontal tracks to individual nets to route a specified net list between two rows of terminals across a two-layer channel in the layout design of LSI chips.
Abstract: In the layout design of LSI chips, channel routing is one of the key problems. The problem is to route a specified net list between two rows of terminals across a two-layer channel. Nets are routed with horizontal segments on one layer and vertical segments on the other. Connections between two layers are made through via holes. Two new algorithms are proposed. These algorithms merge nets instead of assigning horizontal tracks to individual nets. The algorithms were coded in Fortran and implemented on a VAX 11/780 computer. Experimental results are quite encouraging. Both programs generated optimal solutions in 6 out of 8 cases, using examples in previously published papers. The computation times of the algorithms for a typical channel (300 terminals, 70 nets) are 1.0 and 2.1 s, respectively.

538 citations

Journal ArticleDOI
T.G. Szymanski1
TL;DR: It is shown that an efficient optimal algorithm for interconnecting two rows of points across an intervening channel is unlikely to exist by establishing that this problem is NP-complete.
Abstract: Interconnecting two rows of points across an intervening channel is an important problem in the design of LSI circuits. The most common methodology for producing such interconnections uses two orthogonal layers of parallel conductors and allows wires to "dogleg" arbitrarily. Although effective heuristic procedures are available for routing channels with this methodology, no efficient optimal algorithm has yet been discovered for the general case problem. We show that such an algorithm is unlikely to exist by establishing that this problem is NP-complete.

206 citations

BookDOI
12 Nov 2008
TL;DR: Handbook of Algorithms for Physical Design Automation provides a detailed overview of VLSI physical design automation, emphasizing state-of-the-art techniques, trends and improvements that have emerged during the previous decade.
Abstract: The physical design flow of any project depends upon the size of the design, the technology, the number of designers, the clock frequency, and the time to do the design. As technology advances and design-styles change, physical design flows are constantly reinvented as traditional phases are removed and new ones are added to accommodate changes in technology. Includes a personal perspective from Ralph Otten as he looks back on the major technical milestones in the history of physical design automation. Explore State-of-the-Art Techniques and TrendsHandbook of Algorithms for Physical Design Automation provides a detailed overview of VLSI physical design automation, emphasizing state-of-the-art techniques, trends and improvements that have emerged during the previous decade. After a brief introduction to the modern physical design problem, basic algorithmic techniques, and partitioning, the book discusses significant advances in floorplanning representations and describes recent formulations of the floorplanning problem. The text also addresses issues of placement, net layout and optimization, routing multiple signal nets, manufacturability, physical synthesis, special nets, and designing for specialized technologies. Highly-Focused Information for Next Generation Design Problems Although several books on this topic are currently available, most are either too broad or out of date. Alternatively, proceedings and journal articles are valuable resources for researchers in this area, but the material is widely dispersed in the literature. This handbook pulls together a broad variety of perspectives on the most challenging problems in the field, and focuses on emerging problems and research results.

189 citations