An improved architecture used for FPGA's fast and partial configuration is proposed. It is designed based on a 32 bits wide data bus, which can be controlled by a set of instructions. A partial control register and an address decoding logic are added in this design. Multiple configuration interfaces could be connected in this architecture, making hardware updating fast and convenient. Comparing with Virtex Series FPGA's configuration architecture, produced by Xilinx Corp., which only can configure memory cells by frame, this new architecture could configure any single memory cell in FPGA, offering more flexible configuration operations.

The evolution trend of shrinking feature size and increasing complexity in modern electronics is being slowed down due to physical limits that generate numerous imperfections and defects during fabrication steps or projected life time of the chip. Field Programmable Gate Arrays (FPGAs) are used in complex digital systems mainly due to their reconfigurability and shorter time-to-market. To maintain a high reliability of such systems, FPGAs should be tested thoroughly for defects. FPGA architecture optimization for area saving and better signal routability is an ongoing process which directly impacts the overall FPGA testability, hence the reliability. This thesis presents a complete strategy for test and diagnosis of manufacturing defects in mesh-based FPGAs containing a novel multilevel interconnects topology which promises to provide better area and routability. Efficiency of the proposed test schemes is analyzed in terms of test cost, respective fault coverage and diagnostic resolution.

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An FPGA configuration circuit used for fast and partial configuration

Development of test and diagnosis techniques for hierarchical mesh-based FPGAs

To realize high-density SRAMs, we developed a four-transistor SRAM cell with a newly developed stacked vertical poly-silicon PMOS The vertical poly-silicon PMOS has a gate surrounding a body that forms a channel and yields a drive current of 20 /spl mu/A at 25/spl deg/C Vertical poly-silicon PMOSs are used as transfer MOSs and are stacked over the bulk NMOSs, used as driver MOSs, to reduce the size of a four-transistor SRAM cell As a result, the size of the proposed four-transistor SRAM cell was 38% of that of a six-transistor SRAM cell We also developed an electric-field-relaxation scheme to reduce cell leakage and a dual-word-voltage scheme to improve cell stability By applying these two schemes to the proposed four-transistor SRAM cell, we achieved a 90% reduction in cell leakage and an improvement in cell stability

methods

A low-power four-transistor SRAM cell with a stacked vertical poly-silicon PMOS and a dual-word-voltage scheme

The most charming feature of FPGA is that it is post-fabricated, which means that user can design his own logic onto the chip without the need of tape out. So both design cycle and prototype cost can be greatly reduced. Once the bit file - which is a binary file representing the user designed logic s generated, it should be downloaded into the chip to realize the user logic. This paper deals with the way of loading the bit file into the FPGA chip, which has been taped out with SMIC 0.18mum CMOS process this year. Daisy chain and CRC check circuits are designed in this FPGA chip. We use MODELSIM to verify the design before and after the layout is generated. The area of downloading circuit is less than 3 percent of the whole chip

An FPGA configuration circuit used for fast and partial configuration

Citations

Development of test and diagnosis techniques for hierarchical mesh-based FPGAs

References

A low-power four-transistor SRAM cell with a stacked vertical poly-silicon PMOS and a dual-word-voltage scheme

FPGA Downloading Circuit Design and Implementation

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