Proceedings ArticleDOI
Analysis and optimization of thermal issues in high-performance VLSI
Kaustav Banerjee,Massoud Pedram,Amir H. Ajami +2 more
- pp 230-237
TLDR
It is shown that chip level thermal effects can have a significant impact on large-scale circuit optimization techniques, including the clock-skew minimization scheme, and can influence other physical design problem formulations.Abstract:
This paper provides an overview of various thermal issues in high-performance VLSI with especial attention to their implications for performance and reliability. More specifically, it examines the impact of thermal effects on both interconnect design and electromigration reliability and discusses their impact on the allowable current density limits. Furthermore, it also discusses how thermal and reliability constrained current density limits may conflict with those obtained through purely performance based criterion. Additionally, it is shown that chip level thermal effects can have a significant impact on large-scale circuit optimization techniques, including the clock-skew minimization scheme, and can influence other physical design problem formulations. Finally, high-current interconnect design rules for ESD and I/O circuits are also examined.read more
Citations
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Proceedings ArticleDOI
A new methodology for IC-package thermal co-analysis in 3D IC environment
TL;DR: In this paper, the authors present a new methodology to accurately and efficiently predict power and temperature distribution for 3D ICs in deep sub-micron VLSI, where thermal induced reliability and performance issues such as leakage power and electromigration must be taken into consideration in the system level design.
Proceedings Article
Logi-thermal simulation of digital CMOS ICs with emphasis on dynamic power dissipation
TL;DR: A model to obtain variation of temperature in digital CMOS ICs, resulting from dynamic power dissipation, with use of logic simulation instead of circuit-level simulation to save computation time.
Monte-Carlo Study of Phonon Heat Conduction in Silicon Thin Films
TL;DR: In this article, the role of various phonon modes on thermal conductivity predictions was investigated. But the authors focused on the role in the thermal conductivities of optical phonons.
Proceedings ArticleDOI
Future Prediction of Self-Heating in Short Intra-Block Wires
TL;DR: The attribution analysis clarifies that shrinking wire cross-sectional area as well as low-k material and increased power dissipation deteriorates self-heating, and it can cause a reliability and performance degradation in the future.
Journal ArticleDOI
Bus-driven floorplanning with thermal consideration
Po-Hsun Wu,Tsung-Yi Ho +1 more
TL;DR: A thermal-driven bus-driven floorplanning algorithm is proposed to separate hots spots during the perturbation stage and to keep buses away from hotspots during the routing stage to avoid time-consuming thermal simulations.
References
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Journal ArticleDOI
The Transient Response of Damped Linear Networks with Particular Regard to Wideband Amplifiers
TL;DR: It is found possible to define delay time and rise time in such a way that these quantities can be computed very simply from the Laplace system function of the network.
Journal ArticleDOI
Electromigration—A brief survey and some recent results
TL;DR: In this article, it is shown that positive gradients, in terms of electron flow, of temperature, current density, or ion diffusion coefficient foreshorten conductor life because they present regions where vacancies condense to form voids.
Book
Low Power Digital CMOS Design
TL;DR: The Hierarchy of Limits of Power J.D. Stratakos, et al., and Low Power Programmable Computation coauthored with M.B. Srivastava, provide a review of the main approaches to Voltage Scaling Approaches.
Journal ArticleDOI
Zero skew clock routing with minimum wirelength
TL;DR: In this article, a deferred-merge embedding (DME) algorithm is proposed to construct a clock tree with zero skew while minimizing the total wirelength, which can be applied to either the Elmore or linear delay model.
Proceedings ArticleDOI
Planning for performance
TL;DR: To achieve a non-iterative design flow, it is proposed that early synthesis stages should use "wireplanning" to distribute delays over the functional elements and interconnect, and layout synthesis should use its degrees of freedom to realize those delays.
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