Proceedings ArticleDOI
Analysis and optimization of thermal issues in high-performance VLSI
Kaustav Banerjee,Massoud Pedram,Amir H. Ajami +2 more
- pp 230-237
TLDR
It is shown that chip level thermal effects can have a significant impact on large-scale circuit optimization techniques, including the clock-skew minimization scheme, and can influence other physical design problem formulations.Abstract:
This paper provides an overview of various thermal issues in high-performance VLSI with especial attention to their implications for performance and reliability. More specifically, it examines the impact of thermal effects on both interconnect design and electromigration reliability and discusses their impact on the allowable current density limits. Furthermore, it also discusses how thermal and reliability constrained current density limits may conflict with those obtained through purely performance based criterion. Additionally, it is shown that chip level thermal effects can have a significant impact on large-scale circuit optimization techniques, including the clock-skew minimization scheme, and can influence other physical design problem formulations. Finally, high-current interconnect design rules for ESD and I/O circuits are also examined.read more
Citations
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Proceedings ArticleDOI
Buffered clock tree sizing for skew minimization under power and thermal budgets
TL;DR: This paper studies the clock tree sizing problem for thermal-aware skew minimization under power and thermal budgets and focuses on two kinds of skew, depending on the number of thermal profiles given: skew value and skew range.
Proceedings ArticleDOI
Bus-aware microarchitectural floorplanning
Dae Hyun Kim,Sung Kyu Lim +1 more
TL;DR: A fast performance-aware bus routing algorithm is developed, which is integrated into the floorplanning engine to ensure routability while optimizing other conflicting objectives.
Characterization and Modeling of TSV Based 3-D Integrated Circuits
TL;DR: In this paper, the authors provide an introduction to TSV electrical models, power delivery, and thermal behavior in 3-D integrated circuits, and provide guidelines for designing these evolving heterogeneous 3D systems.
Proceedings ArticleDOI
Analytical thermal placement for VLSI lifetime improvement and minimum performance variation
TL;DR: An effective analytical thermal placement technique is developed, as well as an improved analytical placement technique with a new cell spreading function for improved VLSI lifetime and minimized performance variation.
Patent
Methods and Apparatuses for Circuit Simulation
Khalid Rahmat,Ming Huei Young +1 more
TL;DR: In this article, the inductive branch current variables in terms of node voltage variables are eliminated to generate a linear equation system with a sparse, symmetric and positive definite matrix, which can be solved efficiently using a pre-conditioned conjugate gradient method.
References
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TL;DR: In this article, a deferred-merge embedding (DME) algorithm is proposed to construct a clock tree with zero skew while minimizing the total wirelength, which can be applied to either the Elmore or linear delay model.
Proceedings ArticleDOI
Planning for performance
TL;DR: To achieve a non-iterative design flow, it is proposed that early synthesis stages should use "wireplanning" to distribute delays over the functional elements and interconnect, and layout synthesis should use its degrees of freedom to realize those delays.
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