Proceedings ArticleDOI
Analysis and optimization of thermal issues in high-performance VLSI
Kaustav Banerjee,Massoud Pedram,Amir H. Ajami +2 more
- pp 230-237
TLDR
It is shown that chip level thermal effects can have a significant impact on large-scale circuit optimization techniques, including the clock-skew minimization scheme, and can influence other physical design problem formulations.Abstract:
This paper provides an overview of various thermal issues in high-performance VLSI with especial attention to their implications for performance and reliability. More specifically, it examines the impact of thermal effects on both interconnect design and electromigration reliability and discusses their impact on the allowable current density limits. Furthermore, it also discusses how thermal and reliability constrained current density limits may conflict with those obtained through purely performance based criterion. Additionally, it is shown that chip level thermal effects can have a significant impact on large-scale circuit optimization techniques, including the clock-skew minimization scheme, and can influence other physical design problem formulations. Finally, high-current interconnect design rules for ESD and I/O circuits are also examined.read more
Citations
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Journal ArticleDOI
Thermal-aware 3D Symmetrical Buffered Clock Tree Synthesis
TL;DR: A novel 3D symmetrical buffered clock tree synthesis considering thermal variation is proposed that achieves on average 19% of clock skew reduction compared to existing thermal-aware 3D CTS and is very efficient for circuit reliability.
Proceedings ArticleDOI
Self-consistent power/performance/reliability analysis for copper interconnects
TL;DR: This work compares the maximum allowed current density dictated by electromigration constraints for the two low-k technology options and finds that the temperature excursion at the top metal level (relative to the substrate) increases approximately by a factor of 10 in the first case versus 3 for the second by the year 2016.
Patent
Accurate approximation of resistance in a wire with irregular biasing and determination of interconnect capacitances in VLSI layouts in the presence of Catastrophic Optical Proximity Correction
TL;DR: The Width Bias Calculator (WBC) as mentioned in this paper calculates electrical values by averaging the electrical values to either side of a target wire shape whereby values are approximated for design validation without a significant impact on performance or memory consumption.
Journal ArticleDOI
Parallel Performance Analysis of Cyclic Correntropy for Energy-Efficient Wireless Communications
Savio Rennan Menezes Melo,Herlan Assis Pereira da Silva,Samuel Xavier de Souza,Luiz F. Q. Silveira,Aluisio I. R. Fontes +4 more
TL;DR: In this paper, the authors proposed a strategy to calculate the cyclic correntropy by using parallel processing on multi-core processors in order to decrease energy consumption in spectrum sensing tasks.
Proceedings ArticleDOI
A Complex Integrated Circuit Structure Transformation, Modeling and Simulation Method
Daixing Wang,Wei Wang,Yufeng Jin +2 more
TL;DR: This paper provides a conversion method from circuit file to three dimensional(3D) geometry structure, which can extract the detailed multilayer circuit structure from circuit files in popular circuit design software, and model the circuit structure in finite element simulation software, so as to achieve accurate simulation of high thermal conductivity structure of integrated circuits.
References
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Journal ArticleDOI
The Transient Response of Damped Linear Networks with Particular Regard to Wideband Amplifiers
TL;DR: It is found possible to define delay time and rise time in such a way that these quantities can be computed very simply from the Laplace system function of the network.
Journal ArticleDOI
Electromigration—A brief survey and some recent results
TL;DR: In this article, it is shown that positive gradients, in terms of electron flow, of temperature, current density, or ion diffusion coefficient foreshorten conductor life because they present regions where vacancies condense to form voids.
Book
Low Power Digital CMOS Design
TL;DR: The Hierarchy of Limits of Power J.D. Stratakos, et al., and Low Power Programmable Computation coauthored with M.B. Srivastava, provide a review of the main approaches to Voltage Scaling Approaches.
Journal ArticleDOI
Zero skew clock routing with minimum wirelength
TL;DR: In this article, a deferred-merge embedding (DME) algorithm is proposed to construct a clock tree with zero skew while minimizing the total wirelength, which can be applied to either the Elmore or linear delay model.
Proceedings ArticleDOI
Planning for performance
TL;DR: To achieve a non-iterative design flow, it is proposed that early synthesis stages should use "wireplanning" to distribute delays over the functional elements and interconnect, and layout synthesis should use its degrees of freedom to realize those delays.
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