Proceedings ArticleDOI
Analysis and optimization of thermal issues in high-performance VLSI
Kaustav Banerjee,Massoud Pedram,Amir H. Ajami +2 more
- pp 230-237
TLDR
It is shown that chip level thermal effects can have a significant impact on large-scale circuit optimization techniques, including the clock-skew minimization scheme, and can influence other physical design problem formulations.Abstract:
This paper provides an overview of various thermal issues in high-performance VLSI with especial attention to their implications for performance and reliability. More specifically, it examines the impact of thermal effects on both interconnect design and electromigration reliability and discusses their impact on the allowable current density limits. Furthermore, it also discusses how thermal and reliability constrained current density limits may conflict with those obtained through purely performance based criterion. Additionally, it is shown that chip level thermal effects can have a significant impact on large-scale circuit optimization techniques, including the clock-skew minimization scheme, and can influence other physical design problem formulations. Finally, high-current interconnect design rules for ESD and I/O circuits are also examined.read more
Citations
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Journal ArticleDOI
3-D Thermal-ADI: a linear-time chip level transient thermal simulator
TL;DR: An efficient 3-D transient thermal simulator based on the alternating direction implicit (ADI) method for temperature estimation in a3-D environment, which not only has a linear runtime and memory requirement, but also is unconditionally stable.
Proceedings ArticleDOI
A thermally-aware performance analysis of vertically integrated (3-D) processor-memory hierarchy
Gian Luca Loi,Banit Agrawal,Navin Srivastava,Sheng-Chih Lin,Timothy Sherwood,Kaustav Banerjee +5 more
TL;DR: This work is the first attempt to study the performance benefits of 3D technology under the influence of thermal constraints, and it is shown that the 3D system registers large performance improvement for memory intensive applications.
Patent
Methods and apparatuses for thermal analysis based circuit design
TL;DR: In this paper, a thermal analysis is used to determine the temperature dependent power dissipation of a circuit and the temperature distribution of the circuit resulting from dissipating the heat created by the temperature-dependent power disipation.
Patent
Integrated Circuit Devices and Methods and Apparatuses for Designing Integrated Circuit Devices
TL;DR: In this article, a shielding mesh of at least two reference voltages (e.g., power and ground) is used to reduce both the capacitive coupling and the inductive coupling in routed signal wires in IC chips.
Journal ArticleDOI
Thermal issues in next-generation integrated circuits
TL;DR: In this paper, the authors systematically explore the limits for heat removal from a model chip in various configurations, and identify bottlenecks in the thermal performance of current generation packages and motivate lowering of thermal resistance through the board-side for efficient heat removal to meet ever increasing reliability and performance requirements.
References
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Proceedings ArticleDOI
Effects of non-uniform substrate temperature on the clock signal integrity in high performance designs
TL;DR: Using a novel non-uniform temperature-dependent distributed RC interconnect delay model, the behavior of clock skew in the presence of the substrate thermal gradients is analyzed and some design guidelines are provided to ensure the integrity of the clock signal.
Journal ArticleDOI
Self-consistent solutions for allowed interconnect current density. I. Implications for technology evolution
TL;DR: In this article, the authors studied the self-consistent solutions for the maximum allowed interconnect peak current density j/sub peak/ as a function of wave shape and found that the maximum temperature and j/ sub peak/ solutions monotonically increase as the duty cycle r decreases.
Proceedings ArticleDOI
Reduction of wiring capacitance with new low dielectric SiOF interlayer film for high speed/low power sub-half micron CMOS
TL;DR: In this article, the SiOF film was applied to sub-half micron ULSI to improve the circuit speed of 0.35 /spl mu/m with the scaling trend.
Proceedings ArticleDOI
ESD robustness and scaling implications of aluminum and copper interconnects in advanced semiconductor technology
TL;DR: In this article, a comparison of copper and aluminum interconnects and via ESD robustness and failure mechanisms is shown, with an improvement in the ESD of a Cu-based interconnect system, compared to AI-based Interconnects, in the human body and machine model time regimes.
Journal ArticleDOI
State-of-the-art issues for technology and circuit design of ESD protection in CMOS ICs
TL;DR: In this paper, a review of the state-of-the-art issues for electrostatic discharge (ESD) protection devices is presented, focusing on the impact of technology on ESD design and critical issues facing the ability to achieve good ESD reliability as the technologies advance into the deep sub-micron regimes.
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