Charge transport and storage of low programming voltage SONOS/MONOS memory devices

TLDR: In this article, a model based on two carrier conduction (electrons and holes) at both injecting boundaries (semiconductor bulk and gate electrode) is introduced to interpret the ERASE/WRITE characteristics of scaled SONOS devices.

Abstract: In this paper, a model based on two carrier conduction (electrons and holes) at both injecting boundaries (semiconductor bulk and gate electrode) is introduced to interpret the ERASE/WRITE characteristics of scaled SONOS devices. The amphoteric statistics describe the positive and negative charging of the deep-level traps in the nitride “memory” layer. Scaled SONOS/MONOS (polysilicon-oxide-nitride-oxide-semiconductor)/(metal-oxide- nitride-oxide-semiconductor) transistors and capacitors with the bottom (‘tunnel’) oxide layer thickness around 20 A, the final nitride layer thickness below 100 A, and the top (‘blocking’) oxide layer thickness between 35–50 A, have been fabricated and characterized. The results of the model are consistent with the experimental data, which permits physical insight into the mechanisms of charge injection, transport and storage during the ERASE/WRITE operation. Lattice imaging electron microscopy (TEM), ellipsometry, electrical capacitance, and chemical etchback techniques have been used to determine scaled SONOS/MONOS material parameters. The linear voltage ramp technique, which simultaneously measures the flatband voltage shift and separates the charges at the injecting boundary, and the dynamic pulse techniques of flatband tracking and threshold monitoring, which measure ERASE/WRITE, retention and endurance operations, have been employed to electrically characterize the scaled SONOS/MONOS devices. We have demonstrated a differential, saturated ERASE/WRITE flatband shift of 3.8 V with a ±5 V programming voltage for scaled-down SONOS/MONOS devices with dimensions of 20 A for the tunnel oxide, 50 A for the nitride, and 35 A for the blocking oxide. With ±5 V saturated ERASE/WRITE programming voltages and 10 6 ERASE/WRITE cycles, extrapolated retention gives a projected 10 year 0.5 V memory window at room temperature.