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Journal ArticleDOI

Continuous-Time Pipelined Analog-to-Digital Converters: A Mini-Tutorial

TL;DR: The continuous-time pipelined (CTP) ADC as discussed by the authors is an emerging analog-to-digital converter that combines anti-alias filtering and quantization in a single unit.
Abstract: The continuous-time pipelined(CTP) ADC is an emerging analog-to-digital converter that combines anti-alias filtering and quantization in a single unit. It presents a resistive input impedance making it easy to drive, and places relaxed requirements on amplifiers used in the ADC. The CTP ADC attempts to address many of the challenges of discrete-time pipelined analog-to-digital conversion. This brief is a first-principles introduction to this recent architecture.
Citations
More filters
Proceedings ArticleDOI
09 Aug 2021
TL;DR: In this article, the core parameter of the all-pass filter (APF) topology is specified and tradeoffs concerning signal leakage, transfer function error and robustness to process deviations are shown.
Abstract: A continuous-time (CT) pipelined analog-to-digital converter (ADC) profits mostly from a large inter-stage gain (ISG). This gain is constrained by two major factors: coarse stage quantization noise (QN) and signal leakage. With both being as low as possible, the ISG can be increased while overloading of the fine stage is prevented, leading to the best possible performance. The coarse stage’s QN can only be reduced by increasing its resolution. The signal leakage on the other hand can be adjusted in the analog domain by selecting a suitable all-pass filter (APF) topology and optimizing it. This paper presents several methods to specify the core parameter of the APF, i.e. its nominal delay time T d . Furthermore, the use of an extra low-pass filter (LPF) is investigated and tradeoffs concerning signal leakage, transfer function error and robustness to process deviations are shown.

6 citations

Journal ArticleDOI
TL;DR: In this paper, the authors review and discuss recent advances on the design topologies of RF ADCs, including several innovative architectures and techniques, and compare different techniques on bandwidth, power, and noise.

4 citations

Journal ArticleDOI
TL;DR: In this paper , a three-stage continuous-time pipelined (CTP) ADC is compared with measurements from a 3-stage CTP that targets 70dB SNDR in a 100MHz bandwidth while sampling at 800MS/s.
Abstract: The continuous-time pipelined (CTP) ADC is a promising emerging high-speed analog-to-digital conversion technique that achieves anti-alias filtering and analog-to-digital conversion in one step. Driving such a converter is easy, thanks to its resistive input impedance. RC time-constant shifts, which will occur in practice due to a change in ambient temperature, degrade the performance of such converters. The aim of this work is to understand this phenomenon, quantify the resulting SNDR degradation, and thereby derive design tradeoffs. The theory is compared with measurements from a three-stage CTP that targets 70dB SNDR in a 100MHz bandwidth while sampling at 800MS/s.

2 citations

Journal ArticleDOI
TL;DR: This work proposes the use of non-identical (and appropriately chosen) transfer functions for different stages of the pipeline and demonstrates that the sharp filtering offered by a multi-stage CTP can be exploited to implicitly decimate the output sequence of the converter.
Abstract: The continuous-time pipeline (CTP) analog-to-digital converter is an emerging technique that combines the benefits of pipelining with continuous-time operation. Prior-art multistage CTP ADCs have employed stages with identical transfer functions. This work proposes the use of non-identical (and appropriately chosen) transfer functions for different stages of the pipeline. We investigate the benefits of this approach when compared with conventional techniques. We also demonstrate that the sharp filtering offered by a multi-stage CTP can be exploited to implicitly decimate the output sequence of the converter. This is accomplished by clocking the back-end ADC at a lower rate, and by appropriately modifying the digital reconstruction filters. The implicit-decimation theory is supported with measurement results from a three-stage CTP designed in a 65nm CMOS process. The converter achieves 70.4dB SNDR in a 100MHz bandwidth with its front-end operating at $f_{s}\,{=}\,800$ MHz, while the back-end samples at $f_{s}/2$ .

1 citations

Journal ArticleDOI
TL;DR: An overview of circuits and systems techniques for AI-managed analog/digital interfaces with application in SDR/CR mobile telecom systems and some design trends and challenges are discussed, going from new communications and computing paradigms for AIoT devices and networks, to digital-based/scaling-friendly analog circuit techniques for an efficient digitization.
Abstract: Embedding Artificial Intelligence (AI) in integrated circuits is one of the technology pillars of the so-called digital transformation. Nowadays, the vast majority of electronic devices benefits from digital signal processing to implement more and more functionalities, which can be further enhanced by the action of AI algorithms and artefacts. Moreover, as the analog/digital interfaces are moving closer and closer to the point where the information is either acquired or transmitted, the so-called AI-managed data converters are becoming key building blocks in an increasingly number of interconnected cyberphysical systems–made up of both software and hardware components. Software Defined Radio (SDR) and Cognitive Radio (CR) systems intended for 5G/6G communications are good examples which can benefit from an early digitization managed by AI engines. In this context, this paper presents an overview of circuits and systems techniques for AI-managed analog/digital interfaces with application in SDR/CR mobile telecom systems. Some design trends and challenges are discussed, going from new communications and computing paradigms for AIoT devices and networks, to digital-based/scaling-friendly analog circuit techniques for an efficient digitization. The state of the art on Analog-to-Digital Converters (ADCs) is surveyed, putting emphasis on highly-programmable Sigma-Delta Modulators ($\Sigma\Delta$Ms) as one of the best ADC candidates for SDR/CR transceivers. Some chip examples are shown to illustrate their potential application in AI-enhanced CR end-devices.

1 citations

References
More filters
Book
08 Nov 2004
TL;DR: This chapter discusses the design and simulation of delta-sigma modulator systems, and some of the considerations for implementation considerations for [Delta][Sigma] ADCs.
Abstract: Chapter 1: Introduction.Chapter 2: The first-order delta-sigma modulator.Chapter 3: The second-order delta-sigma modulator.Chapter 4: Higher-order delta-sigma modulation.Chapter 5: Bandpass and quadrature delta-sigma modulation.Chapter 6: Implementation considerations for [Delta][Sigma] ADCs.Chapter 7: Delta-sigma DACs.Chapter 8: High-level design and simulation.Chapter 9: Example modulator systems.Appendix A: Spectral estimation.Appendix B: The delta-sigma toolbox.Appendix C: Noise in switched-capacitor delta-sigma data converters.

2,200 citations

Journal ArticleDOI
TL;DR: A 0-3 multi-stage noise-shaping (MASH) ADC that achieves a dynamic range of 88 dB over 53 MHz signal bandwidth and achieves the high thermal noise power efficiency of a continuous-time feedforward ΔΣ modulator and the flat signal transfer function of a flash ADC is presented.
Abstract: We present design and measurement details for a 0-3 multi-stage noise-shaping (MASH) ADC that achieves a dynamic range of 88 dB over 53 MHz signal bandwidth The ADC utilizes a zeroth-order front-end, ie, a 17-level flash ADC, to perform a coarse quantization and a third-order 7-level continuous-time ΔΣ back-end to digitize the residue error of the front-end The ADC achieves the high thermal noise power efficiency of a continuous-time feedforward ΔΣ modulator and the flat signal transfer function of a flash ADC The test chip, implemented in a 28 nm CMOS process, clocks at 32 GHz The average noise spectral density with small input signals is -167 dBFS/Hz and the dynamic range is 88 dB The test chip ADC consumes a total power of 235 mW from triple power supplies of 09/18/-10 V The thermal-noise figure-of-merit, defined as FOM = DR + 10log 10 (BW/P) is 1716 dB

64 citations

Journal ArticleDOI
TL;DR: This paper presents a practical way to achieve both wide signal bandwidth and high dynamic range in a continuous- time (CT) delta-sigma modulator by increasing the effective order of the noise transfer function based on a sturdy multi-stage noise-shaping (SMASH) architecture.
Abstract: This paper presents a practical way to achieve both wide signal bandwidth and high dynamic range in a continuous- time (CT) delta-sigma modulator. Quantization noise is suppressed aggressively by increasing the effective order of the noise transfer function based on a sturdy multi-stage noise-shaping (SMASH) architecture. The proposed CT SMASH architecture has a much wider signal bandwidth which was limited in the discrete-time (DT) SMASH architecture due to the inherent sampling frequency limitation of DT implementation. Furthermore, the proposed CT SMASH architecture provides better quantization noise suppression by more completely canceling the quantization noise from the $1{\hbox {st}}$ -loop. The CT SMASH architecture is implemented with several efficient circuit techniques suitable for high operation speed. As a result, the prototype fabricated in 28 nm CMOS achieves DR of 85 dB, peak SNDR of 74.9 dB, SFDR of 89.3 dBc, and Schreier FOM of 172.9 dB over a 50 MHz bandwidth at a 1.8 GHz sampling frequency.

52 citations

Journal ArticleDOI
TL;DR: This paper presents a continuous-time (CT) multi-stage noise-shaping (MASH) ADC in 28 nm CMOS that uses a first-order front-end stage and a second-order back- end stage to digitize the quantization noise of the coarse flash ADC inside the front- end.
Abstract: This paper presents a continuous-time (CT) multi-stage noise-shaping (MASH) ADC in 28 nm CMOS. The MASH ADC uses a first-order front-end stage to digitize the input signal and a second-order back-end stage to digitize the quantization noise of the coarse flash ADC inside the front-end. An RC lattice filter and a current-steering DAC are utilized to extract the front-end coarse quantization residue. The prototype MASH ADC chip built in a 28 nm CMOS process is clocked at 8 GHz with an OSR of 8.6, providing a signal bandwidth of 465 MHz. The ADC achieves a DR of 72 dB and an average small-signal NSD of −160 dBFS/Hz. The peak SNR is 68 dB and the peak SNDR is 67 dB. The IM3 is −88 dBFS with two −9 dBFS tones at the band edge. The ADC consumes 890 mW of power from +1.8/1.0/-1.0 V supplies and achieves a thermal noise FOM of 159 dB.

47 citations

Proceedings ArticleDOI
25 Feb 2016
TL;DR: This work looks to extend the applicability of high-speed ADCs by digitizing wireless communications bands up to 4GHz with a high level of spectral purity by reporting a new ADC that achieves noise performance of over 60dBFS and linearity performance of 64dBc at 1.842GHz input frequency.
Abstract: The performance and power consumption of high-speed ADCs has advanced such that some receiver architectures can directly sample the input without down-conversion. This work looks to extend the applicability of such high-speed ADCs by digitizing wireless communications bands up to 4GHz with a high level of spectral purity. Fabricated in foundry 65nm CMOS and operating up to 4GS/s with power consumption of 2.2W, the reported ADC achieves noise performance of over 60dBFS and linearity performance of 64dBc at 1.842GHz input frequency. At 3.8GHz input frequency, SNR is dominated by aperture jitter of 50fs and two-tone IMD3 is >60dBFS.

30 citations