Journal ArticleDOI
Continuous-Time Pipelined Analog-to-Digital Converters: A Mini-Tutorial
Shanthi Pavan,Hajime Shibata +1 more
TLDR
The continuous-time pipelined (CTP) ADC as discussed by the authors is an emerging analog-to-digital converter that combines anti-alias filtering and quantization in a single unit.Abstract:
The continuous-time pipelined(CTP) ADC is an emerging analog-to-digital converter that combines anti-alias filtering and quantization in a single unit. It presents a resistive input impedance making it easy to drive, and places relaxed requirements on amplifiers used in the ADC. The CTP ADC attempts to address many of the challenges of discrete-time pipelined analog-to-digital conversion. This brief is a first-principles introduction to this recent architecture.read more
Citations
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Proceedings ArticleDOI
Minimizing Signal-Dependent Residue in CT Pipelined ADCs
TL;DR: In this article, the core parameter of the all-pass filter (APF) topology is specified and tradeoffs concerning signal leakage, transfer function error and robustness to process deviations are shown.
Journal ArticleDOI
Radio frequency analog-to-digital converters: Systems and circuits review
TL;DR: In this paper, the authors review and discuss recent advances on the design topologies of RF ADCs, including several innovative architectures and techniques, and compare different techniques on bandwidth, power, and noise.
Journal ArticleDOI
Analysis of RC Time-Constant Variations in Continuous-Time Pipelined ADCs
TL;DR: In this paper , a three-stage continuous-time pipelined (CTP) ADC is compared with measurements from a 3-stage CTP that targets 70dB SNDR in a 100MHz bandwidth while sampling at 800MS/s.
Journal ArticleDOI
Improved Multistage Continuous-Time Pipelined Analog-to-Digital Converters and the Implicit Decimation Property
TL;DR: This work proposes the use of non-identical (and appropriately chosen) transfer functions for different stages of the pipeline and demonstrates that the sharp filtering offered by a multi-stage CTP can be exploited to implicitly decimate the output sequence of the converter.
Journal ArticleDOI
AI-Managed Cognitive Radio Digitizers
TL;DR: An overview of circuits and systems techniques for AI-managed analog/digital interfaces with application in SDR/CR mobile telecom systems and some design trends and challenges are discussed, going from new communications and computing paradigms for AIoT devices and networks, to digital-based/scaling-friendly analog circuit techniques for an efficient digitization.
References
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Book
Understanding Delta-Sigma Data Converters
TL;DR: This chapter discusses the design and simulation of delta-sigma modulator systems, and some of the considerations for implementation considerations for [Delta][Sigma] ADCs.
Journal ArticleDOI
A Continuous-Time 0–3 MASH ADC Achieving 88 dB DR With 53 MHz BW in 28 nm CMOS
TL;DR: A 0-3 multi-stage noise-shaping (MASH) ADC that achieves a dynamic range of 88 dB over 53 MHz signal bandwidth and achieves the high thermal noise power efficiency of a continuous-time feedforward ΔΣ modulator and the flat signal transfer function of a flash ADC is presented.
Journal ArticleDOI
A Continuous-Time Sturdy-MASH $\Delta\Sigma$ Modulator in 28 nm CMOS
TL;DR: This paper presents a practical way to achieve both wide signal bandwidth and high dynamic range in a continuous- time (CT) delta-sigma modulator by increasing the effective order of the noise transfer function based on a sturdy multi-stage noise-shaping (SMASH) architecture.
Journal ArticleDOI
A 72 dB-DR 465 MHz-BW Continuous-Time 1-2 MASH ADC in 28 nm CMOS
Yunzhi Dong,Jialin Zhao,Wenhua William Yang,Trevor Clifford Caldwell,Hajime Shibata,Zhao Li,Richard Schreier,Qingdong Meng,Jose Barreiro Silva,Donald Paterson,Jeffrey Gealow +10 more
TL;DR: This paper presents a continuous-time (CT) multi-stage noise-shaping (MASH) ADC in 28 nm CMOS that uses a first-order front-end stage and a second-order back- end stage to digitize the quantization noise of the coarse flash ADC inside the front- end.
Proceedings ArticleDOI
27.5 A 4GS/s time-interleaved RF ADC in 65nm CMOS with 4GHz input bandwidth
Matt Straayer,Jim Bales,Dwight Birdsall,Denis C. Daly,Phillip Elliott,Bill Foley,Roy Mason,Vikas Singh,Xuejin Wang +8 more
TL;DR: This work looks to extend the applicability of high-speed ADCs by digitizing wireless communications bands up to 4GHz with a high level of spectral purity by reporting a new ADC that achieves noise performance of over 60dBFS and linearity performance of 64dBc at 1.842GHz input frequency.