Journal ArticleDOI
Design Methodology of DC Power Cycling Test Setup for SiC MOSFETs
Fei Yang,Enes Ugur,Bilal Akin +2 more
TLDR
Experimental results show that an accurate measurement can be achieved with the design considerations regarding precise parameter measurement of the device’s parameter, and the practical issues affecting the measurement accuracy in a multiple-phase setup are investigated.Abstract:
The long-term reliability concerns regarding the latest power devices, e.g., silicon carbide (SiC) MOSFETs, need to be well understood for their rapid and widespread deployment in industrial applications. As an effective reliability assessment, the dc power cycling test is one of the most realistic procedures providing accelerated lifetime tests. In this paper, a dc power cycling setup for SiC power MOSFETs is proposed, and the design methodology is generalized for practicing engineers. At first, the aging-independent junction temperature measurement method is identified to eliminate the laborious recalibration process. Specifically, the electrical parameter changes of commercial SiC MOSFETs are evaluated in a power cycling test. It is observed experimentally that the body diode’s voltage drop at low current and negative gate bias is unaffected by the device/package degradation. Therefore, it is selected for $T_{j}$ measurement in the proposed setup. Following that, the design considerations regarding precise parameter measurement of the device’s parameter are presented. The transient behavior of the proposed test setup is analyzed, and a simulation model is built in LTspice. Based on the model, the effects of gate timing control and paralleled capacitors are investigated for realizing accurate measurements, and the simulation results are verified experimentally in a prototype. In addition, considering the measurement delay in the conditioning circuits and the common-mode noise, the practical issues affecting the measurement accuracy in a multiple-phase setup are investigated in the experiment. Experimental results show that an accurate measurement can be achieved with the design considerations.read more
Citations
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Journal ArticleDOI
Overview of Real-Time Lifetime Prediction and Extension for SiC Power Converters
TL;DR: In this paper, the authors provide a comprehensive overview, address existing challenges, and unfold new research opportunities regarding the SiC power converter real-time lifetime prediction and extension, including component-level failure modes and mechanisms.
Journal ArticleDOI
Evaluation of Aging's Effect on Temperature-Sensitive Electrical Parameters in SiC mosfets
Fei Yang,Enes Ugur,Bilal Akin +2 more
TL;DR: In this article, the authors investigated the aging's impacts on various temperature sensitive electrical parameters (TSEPs) in SiC mosfets and found that the package degradation's impact on TSEPs was more significant than the gate oxide instability.
Journal ArticleDOI
Turn- on Delay Based Real-Time Junction Temperature Measurement for SiC MOSFETs With Aging Compensation
TL;DR: It is shown that the proposed circuit provides an accurate real-time online junction temperature measurement for SiC MOSFETs, which can be deployed to improve the power converters’ reliability.
Journal ArticleDOI
Data-Driven Approach for Fault Prognosis of SiC MOSFETs
Weiqiang Chen,Lingyi Zhang,Krishna R. Pattipati,Ali M. Bazzi,Shailesh N. Joshi,Ercan M. Dede +5 more
TL;DR: This article proposes an unsupervised learning approach for fault prognosis of silicon carbide (SiC) mosfets that utilizes the changing trend of a device's voltage, current, temperature, and other device characteristics with its degradation.
Journal ArticleDOI
Temperature-Independent Gate-Oxide Degradation Monitoring of SiC MOSFETs Based on Junction Capacitances
TL;DR: In this paper, two temperature-independent precursors (Miller capacitance and gate-source capacitance changes) are proposed for gate-oxide degradation monitoring of SiC MOSFET s.
References
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Journal ArticleDOI
Basic Mechanisms of Threshold-Voltage Instability and Implications for Reliability Testing of SiC MOSFETs
TL;DR: In this article, a review of the basic mechanisms affecting the stability of the threshold voltage in response to bias-temperature stress is presented in terms of the charging and activation of near-interfacial oxide traps.
Journal ArticleDOI
Time Dependence of Bias-Stress-Induced SiC MOSFET Threshold-Voltage Instability Measurements
Aivars J. Lelis,Daniel B. Habersat,Ronald Green,Aderinto Ogunniyi,M. Gurfinkel,J. Suehle,Neil Goldsman +6 more
TL;DR: In this article, the authors observed significant instability in the threshold voltage of 4H-SiC metal-oxide-semiconductor field effect transistors due to gate-bias stressing.
Journal ArticleDOI
A 1200-V, 60-A SiC MOSFET Multichip Phase-Leg Module for High-Temperature, High-Frequency Applications
TL;DR: In this paper, a high-temperature, high-frequency, wire-bond-based multichip phase-leg module was designed, fabricated, and fully tested using paralleled Silicon Carbide (SiC) MOSFETs.
Journal ArticleDOI
Real-Time Temperature Estimation for Power MOSFETs Considering Thermal Aging Effects
TL;DR: In this paper, a real-time power-device temperature estimation method that monitors the power MOSFET's junction temperature shift arising from thermal aging effects and incorporates the updated electrothermal models of power modules into digital controllers is presented.
Journal ArticleDOI
Threshold voltage peculiarities and bias temperature instabilities of SiC MOSFETs
TL;DR: A new measure-stress-measure procedure for BTI evaluation of SiC MOSFETs is proposed which allows distinguishing between reversible threshold voltage hysteresis and more permanent threshold voltage drift (BTI).