Design of Memristor – CMOS based logic gates and logic circuits

TLDR: The transient response of Hybrid CMOS-memristor based logic gates and different adder circuits and multiplier circuit are performed in Cadence 180nm technology.

Abstract: Recent researches are mostly focused on technology scaling as well as device size minimization design techniques following Moore’s law. Conventional computing architectures are unable to fulfill modern application demands. Memristor is a promising alternative device which has been developed by many researchers [2] to draw attention of its structure for numerous applications which includes computational logic, memory implementations and neuromorphic systems. This paper emphasizes the basic properties of memristor at the device level. Different digital circuits have been designed for logic operations and DSP applications. Design methodologies are developed for proper circuit design, and circuit parameters are taken from a very detailed device model and optimization techniques. The transient response of Hybrid CMOS-memristor based logic gates and different adder circuits (i.e, half adder, full adder, carry-save adder) and multiplier circuit are performed in Cadence 180nm technology.