Proceedings ArticleDOI
Dynamic flip-flop with improved power
Nikola Nedovic,Vojin G. Oklobdzija +1 more
- pp 323-326
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TLDR
In this paper, an improved design of a dynamic flip-flop is presented, which overcomes the problem of the glitch at the output and improves power-delay product for about 27%, while preserving logic embedding property.Abstract:
An improved design of a dynamic flip-flop is presented. The proposed design overcomes the problem of the glitch at the output and improves power-delay product for about 27%, while preserving logic embedding property. This is accomplished by equalizing the t/sub pLH/ and t/sub pHL/ of the flip-flop and careful design of keeper elements in the circuit. New design introduces insignificant area increase.read more
Citations
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Journal ArticleDOI
Dual-edge triggered storage elements and clocking strategy for low-power systems
TL;DR: The simulated results show that by halving the clock frequency, dual-edge clocking strategy can save about 50% of the power consumed by the clock distribution network, and relax the design of clock distribution system, while paying virtually no penalty in throughput.
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General Strategies to Design Nanometer Flip-Flops in the Energy-Delay Space
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Low power integrated scan-retention mechanism
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Low-power circuits and technology for wireless digital systems
Stephen V. Kosonocky,Azeez Bhavnagarwala,Ken K. Chin,George D. Gristede,A.-M. Haen,W. Hwang,M. B. Ketchen,Suhwan Kim,Daniel R. Knebel,Kevin Wilson Warren,Victor Zyuban +10 more
TL;DR: Circuit techniques for low-power communication systems which exploit the capabilities of advanced CMOS technology are described and described.
References
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Journal ArticleDOI
Comparative analysis of master-slave latches and flip-flops for high-performance and low-power systems
TL;DR: A new simulation and optimization approach is presented, targeting both high-performance and power budget issues, and the analysis approach reveals the sources of performance and power-consumption bottlenecks in different design styles.
Proceedings ArticleDOI
Flow-through latch and edge-triggered flip-flop hybrid elements
TL;DR: This paper describes a hybrid latch-flipflop (HLFF) timing methodology aimed at a substantial reduction in latch latency and clock load.
Proceedings ArticleDOI
Semi-dynamic and dynamic flip-flops with embedded logic
TL;DR: A family of semi-dynamic and dynamic edge-triggered flip-flops to be used with static and dynamic circuits, respectively, used in the UltraSPARC-III microprocessor.