Journal ArticleDOI
Efficient Shuffle Network Architecture and Application for WiMAX LDPC Decoders
TLDR
A new algorithm that can efficiently generate all the control signals for the shuffle network used in flexible low-density parity-check (LDPC) decoders is proposed and a low-complexity reconfigurable shuffle network architecture for flexible LDPC decmoders is developed.Abstract:
In this brief, a new algorithm that can efficiently generate all the control signals for the shuffle network used in flexible low-density parity-check (LDPC) decoders is proposed. Employing the proposed algorithm, the hardware complexity of the controller of shuffle networks using the Benes network structure can be significantly reduced. In addition, a low-complexity reconfigurable shuffle network architecture for flexible LDPC decoders is developed. Both the Benes network and the controller can be tailored to fit specific applications. Consequently, an efficient shuffle network for WiMAX LDPC decoders is presented. Synthesis results demonstrate that with the SMIC 0.18-mum complementary metal-oxide-semiconductor process, the total gate count of the proposed shuffle network is only 16 000. The area saving is between 26.6% and 71.1% compared to related works in the literature.read more
Citations
More filters
Journal ArticleDOI
Memory System Optimization for FPGA-Based Implementation of Quasi-Cyclic LDPC Codes Decoders
TL;DR: Two specific optimizations called vectorization and folding are presented to take advantage of the configurable data-width and depth of embedded memory in an FPGA to improve the throughput of a decoder for quasi-cyclic LDPC codes.
Journal ArticleDOI
QSN—A Simple Circular-Shift Network for Reconfigurable Quasi-Cyclic LDPC Decoders
TL;DR: Analytical models of the critical-path and datapath complexity for arbitrary-sized submatrices are presented and it is proved that the QSN indeed generates all the output combinations required for implementing reconfigurable QC-LDPC decoders.
Journal ArticleDOI
Design of a Multimode QC-LDPC Decoder Based on Shift-Routing Network
Chih-Hao Liu,Chien-Ching Lin,Shau-Wei Yen,Chih-Lung Chen,Hsie-Chia Chang,Chen-Yi Lee,Yarsun Hsu,Shyh-Jye Jou +7 more
TL;DR: A reconfigurable message-passing network is proposed to facilitate message transportation in decoding multimode quasi-cyclic low-density parity-check (QC-LDPC) codes by exploiting the shift-routing network (SRN) features.
Journal ArticleDOI
A Multimode Shuffled Iterative Decoder Architecture for High-Rate RS-LDPC Codes
TL;DR: It is revealed that the structural properties inherent in an LDPC code constructed based on a Reed-Solomon code with two information symbols can be adopted in the design of configurable permutators and is used to mitigate the increase in implementation complexity for the multimode function.
Patent
Decoder and decoding method for low-density parity check codes constructed based on reed-solomon codes
TL;DR: In this paper, the variable nodes are partitioned into several groups, and each group is processed sequentially in order to shorten the critical-path delay and, hence, increase the maximum operating frequency.
References
More filters
Journal ArticleDOI
Optimal rearrangeable multistage connecting networks
TL;DR: By using a large number of stages, these designs achieve a far greater combinatorial efficiency than has been attained heretofore.
Journal ArticleDOI
Near-Shannon-limit quasi-cyclic low-density parity-check codes
TL;DR: This letter presents two classes of quasi-cyclic low-density parity-check codes that perform close to the Shannon limit.
Journal ArticleDOI
Low-Complexity High-Speed Decoder Design for Quasi-Cyclic LDPC Codes
Zhongfeng Wang,Zhiqiang Cui +1 more
TL;DR: Enhanced partially parallel decoding architectures for quasi-cyclic low density parity check (QC-LDPC) codes are proposed to linearly increase the throughput of conventional partially parallel decoders through introducing a small percentage of extra hardware.
Journal ArticleDOI
Implementation of a Flexible LDPC Decoder
TL;DR: This work presents a novel formulation of the decoding algorithm that strongly simplifies internal communication requirements and enables the development of decoders supporting generally defined LDPC codes, and the resulting architecture is tailored to decode both IEEE 802.11n and IEEE802.16eLDPC codes.