Open AccessProceedings Article
Fast frequency acquisition phase-frequency detectors for GSa/s phase-locked loops
Mozhgan Mansuri,D. Liu,Chih-Kong Ken Yang +2 more
- pp 333-336
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TLDR
In this paper, two techniques for phase-frequency detectors (PFDs) with higher operating frequencies (periods of less than 8x the delay of a fan-out-4 inverter (FO-4)) and faster frequency acquisition are described.Abstract:
This paper describes two techniques for designing phase-frequency detectors (PFDs) with higher operating frequencies (periods of less than 8x the delay of a fan-out-4 inverter (FO-4)) and faster frequency acquisition. Prototypes designed in 0.25-µm CMOS process exhibit operating frequencies of 1.25 GHz ( = 1/(8 ċ FO-4) ) and 1.5 GHz ( = 1/(6.7 ċ FO-4) ) for two techniques respectively whereas a conventional PFD operates < 1 GHz ( = 1/(10 ċ FO-4) ). The two proposed PFDs achieve a capture range of 1.7x and 1.2x the conventional design.read more
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A Digital Calibration Technique for Charge Pumps in Phase-Locked Systems
TL;DR: A digital technique is adopted to calibrate the current mismatch of the charge pump (CP) in phase-locked systems, where there is no extra replica CP needed and the additional power consumption and digital switching noise from the calibration circuits are turned off once the calibration is finished.
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Analog Filter Design Using Ring Oscillator Integrators
TL;DR: This work proposes applying ring oscillator integrators (ROIs) in the design of high order analog filters to achieve infinite DC gain at low supply voltages independent of transistor non-idealities and imperfections such as finite output impedance.
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A 6.3-9-GHz CMOS fast settling PLL for MB-OFDM UWB applications
TL;DR: In this paper, a CMOS phase-locked loop (PLL) which synthesizes frequencies between 6.336 and 8.976 GHz in steps of 528 MHz and settles in approximately 150 ns is presented.
References
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Proceedings ArticleDOI
Flow-through latch and edge-triggered flip-flop hybrid elements
TL;DR: This paper describes a hybrid latch-flipflop (HLFF) timing methodology aimed at a substantial reduction in latch latency and clock load.
Proceedings ArticleDOI
Adaptive bandwidth DLLs and PLLs using regulated supply CMOS buffers
TL;DR: In this paper, a technique for designing DLLs and PLLs using CMOS buffers with a regulated supply is presented, which achieves a wide bandwidth that tracks the operating frequency, a constant damping factor, large operating range and low noise sensitivity.
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