FPGA Design Methodology for Industrial Control
Systems – a Review
*
Eric Monmasson,
S
ENIOR
M
EMBER
,
IEEE,
**
Marcian Cirstea,
S
ENIOR
M
EMBER
,
IEEE
*
SATIE, Université de Cergy-Pontoise, rue d’Eragny, Neuville-sur-Oise, 95031 Cergy-Pontoise, France
Phone: +33 (0)1 34 25 68 91, Fax: +33 (0)1 34 25 69 01, E-Mail: eric.monmasson@u-cergy.fr
**
Department of Design and Technology,
Anglia Ruskin University, East Road, Cambridge, CB1 1PT, England, UK,
Phone: +44 (0)1223 363271 ext.2184, Fax: +44 (0)1223-417711, E-Mail: marcian.cirstea@anglia.ac.uk
Abstract
– This paper reviews the state of the art of Field
Programmable Gate Array (FPGA) design methodologies
with a focus on Industrial Control System applications.
The paper starts with an overview of FPGA technology
development, followed by a presentation of design
methodologies, development tools and relevant CAD
environments, including the use of portable Hardware
Description Languages and System Level Programming /
Design tools. They enable a holistic functional approach
with the major advantage of setting up a unique modeling
and evaluation environment for complete industrial
electronics systems.
Three main design rules are then presented. These are:
algorithm refinement, modularity and systematic search
for the best compromise between the control performance
and the architectural constraints. An overview of
contributions and limits of FPGAs is also given, followed
by a short survey of FPGA-based intelligent controllers for
modern industrial systems.
Finally, two complete and timely case studies are
presented to illustrate the benefits of an FPGA-
implementation when using the proposed system modeling
and design methodology. These consist of the Direct
Torque Control for induction motor drives and the control
of a diesel driven synchronous stand-alone generator with
the help of fuzzy logic.
Index Terms: FPGAs, Industrial Control Systems, VHDL,
Design Methodologies, Programmable Architectures, SoC
I.
I
NTRODUCTION
Fast progress of Very Large Scale Integration (VLSI)
technology and Electronic Design Automation (EDA)
techniques in recent years has created an opportunity for the
development of complex and compact high performance
controllers for industrial electronic systems [1]. Nowadays,
the design engineer is using modern EDA tools to create,
simulate and verify a design, and, without committing to
hardware, can quickly evaluate complex systems and ideas
with very high confidence in the “right first time” correct
operation of the final product.
Speed performance of new components and flexibility
inherent of all programmable solutions give today many
opportunities in the field of digital implementation for
industrial control systems. This is especially true with
software solutions such as microprocessors or DSPs (Digital
Signal Processors) [3]. However, specific hardware
technologies such as Field Programmable Gate Arrays
(FPGAs) can also be considered as an appropriate solution
in order to boost the performance of controllers. Indeed,
these generic components combine low cost development
(thanks to their re-programmability), use of convenient
software tools and more and more significant integration
density [4]-[8]. FPGA technology is now considered by an
increasing number of designers in various fields of
application such as wired and wireless telecommunications
[9], image and signal processing [10], [11], where the
always more demanding data throughputs take advantage of
the ever increasing density of the chips. Still, more recently,
other application fields are in growing demand, such as
medical equipment [12], robotics [13]-[15], automotive [16]
and space and aircraft embedded control systems [17]. For
these embedded applications, reduction of the power
consumption [18], thermal management and packaging [19],
reliability [20] and protection against solar radiations [21]
are of prime importance. Finally, industrial electrical control
systems are also of great interest because of the ever
increasing level of expected performance, while at the same
time reducing the cost of the control systems [22]. This last
sector is especially targeted by the case studies presented
briefly in this review paper. Indeed, FPGAs have already
been used with success in many different electric system
applications such as power converter control (PWM
inverters [23], [24], power factor correction [25], multilevel
converters [26], [27], matrix converters [28], [29], soft
switching [30], [31], and STATCOM [32]) and electrical
machines control (induction machine drives [33]-[39], SRM
drives [40], motion control [41], [42], multi-machines
systems [43], Neural Network control of induction motors
[44], Fuzzy Logic control of power generators [45], speed
measurement [46]). This is because an FPGA-based
implementation of controllers can efficiently answer current
and future challenges of this field. Amongst them, we can
quote:
- Decrease of the cost for at least three reasons: the use of an
architecture based only on the specific needs of the
algorithm to implement, the application of highly advanced
and specific methodologies improving implementation time
also called "time to market", and the expected development
in VLSI design that will allow integrating a full control
system with its analog interface in a single chip, also called
System-on-a-Chip (SoC);
- Confidentiality, a specific architecture, integrating the
know-how of a company, is not easily duplicable;
- Embedded systems with many constraints as in aircraft
applications, like limited power consumption, thermal
consideration, reliability and Single Event Upset (SEU)
protection;
- Improvement of control performance. For example,
execution time can be dramatically reduced by designing
dedicated parallel architectures, allowing FPGA-based
controllers to reach the level of performance of their analog
counterparts without their drawbacks (parameter drifts, lack
of flexibility). Besides, an FPGA-based controller can be
adapted in run-time to the needs of the plant by dynamically
reconfiguring it. These points will be discussed further in
section V.
This article aims to provide an overview of the use of
FPGAs in industrial control systems. Generic FPGA
architectures and Computer Aided Design (CAD)
environment characterizing them are presented. Benefits of
using portable Hardware Description Languages (HDLs) are
discussed, then, the holistic approach is explained. It extends
the traditional use of High Level Programming Languages
and HDLs [2] to encompass the holistic modeling of
industrial electronic systems. The outcome is a design
environment that allows all functional aspects of the system
to be considered simultaneously, therefore increasing the
determinism of the system, minimizing response time and
maximizing operational performance in order to achieve
high efficiency and power quality, while simultaneously
allowing the rapid prototyping of digital controllers on
FPGA hardware development platforms.
Major design rules are given, consisting of control
algorithm refinement, application of a reuse methodology,
which allows capitalizing the design efforts and optimization
of the modules in terms of performance with the help of the
Algorithm Architecture “Adequation” (A
3
). The authors
then analyze, in the present industrial environment, the
contributions and the limits of using FPGAs in electrical
system controllers. A short survey on intelligent FPGA-
based controllers is also presented.
Finally, two case studies are discussed to illustrate
benefits of an FPGA-implementation when using the
proposed design methodology: i) Direct Torque Control
(DTC) system for Induction Motor, ii) Fuzzy Logic digital
controller for a diesel driven stand alone power generator.
II.
D
ESCRIPTION OF
FPGA
S AND THEIR
D
EVELOPMENT
T
OOLS
A. FPGA Generic Architecture Description
FPGAs belong to the wide family of programmable logic
components [4]-[8]. An FPGA is defined as a matrix of
configurable logic blocks (combinatorial and/or sequential),
linked to each others by an interconnection network which is
entirely reprogrammable. The memory cells control the logic
blocks as well as the connections so that the component can
fulfill the required application specifications. Several
configurable technologies exist. Amongst them, only those
which are reprogrammable (Flash, EPROM, SRAM) are of
interest since they allow the same flexibility as that of a
microprocessor. Therefore, the rest of the paper will discuss
only the SRAM-based FPGA technology [6]-[7], by far the
most widespread [47]. However, the Flash-based technology
[8], although it does not allow the same number of
reconfiguration cycles by an order of magnitude, it is of
interest for some stringent niche applications such as space
and aircraft industries. Indeed, Flash technology preserves
the configuration of the FPGA when the power is off and, as
a consequence, the chip is ready to operate as soon as it is
powered up. The generic architecture of a SRAM-based
FPGA is presented in Fig. 1 [48].
The most recent FPGAs are produced using a 65-nm
copper process. Their density can reach more than 10
million equivalent gates per chip with clock system
frequencies of more than 500 MHz. However, it is important
to note that this kind of information is only accurate for a
short while, as technology continues to move forward. The
two main FPGA manufacturers are Altera and Xilinx [6]-[7].
Fig. 1. Generic architecture of an FPGA.
The FPGA generic architecture is composed of a matrix
of configurable logic blocks (CLBs), where the number of
rows and columns are now reaching, for the largest devices,
192x116. This matrix core is bordered by a ring of
configurable input/output blocks (IOBs), whose number can
reach 1000 user IOBs. Finally, all these resources
communicate amongst themselves through a programmable
interconnection network.
More recently, it has also been observed inside these
architectures, the introduction of some dedicated blocks such
as RAM, DSP accelerators (hardwired multipliers with
corresponding accumulators, high-speed clock management
circuitry, serial transceivers), embedded hard processor
cores such as PowerPC or ARM [6]-[8] and soft processor
cores such as Nios [6] or Microblaze [7], [70]. Also very
interesting for control applications is the recent integration
of an analog-to-digital converter in the Fusion component
from Actel [8]. However, this SoC trend, does not replace
Configurable
Input/Output
Block
Configurable
Logic Block
Interconnection
Programmable
Network
the former generic architecture but it can be seen as a
complement to this original matrix.
- Configurable Logic Blocks: Their structures include 2,
4 or more logic cells, also called logic elements. The
structure of a logic cell, which can be considered as the basic
grain of the FPGA, is presented in Fig.2.
Fig. 2. Logic cell structure
It consists of a 4-bit look-up table (LUT), which can be
configured either as a (16x1) ROM, RAM or a
combinatorial function. A carry look-ahead data path is also
included, in order to build efficient arithmetic operators.
Finally, a D-Type Flip-Flop, with all its control inputs
(synchronous or asynchronous set/reset, enable), allows
registering the output of the logic cell. Such an architecture
corresponds to a micro state-machine, since the registered
output can be configured as an input of the same logic cell.
B. Hardware Description Languages and FPGAs
Originally, FPGAs were only used to integrate glue-logic
usually devoted to TTL basic logic circuits. Applications
were described with the help of simple CAD schematic
tools. Today, FPGAs are more and more used to implement
complex functions. For example, it is not unusual to
implement in a single FPGA a complete digital system
including an Arithmetic Logic Unit (ALU), memories,
communication units, and so on.
This evolution has its origin in the recent advances in
VLSI but it is also due to the development of appropriate
design tools and methods, which were initially reserved to
the world of the Application Specific Integrated Circuits
(ASICs). These tools are mostly based on Hardware
Description Languages (HDLs) such as Very high speed
integrated circuits (Vhsic) Hardware Description Language
(VHDL) [2], [49] or Verilog [50]. The existence of IEEE
standards [51] has spread the use of HDLs and has allowed
the creation and the development of high performance CAD
tools in the field of microelectronics. Thus, the designer can
take advantage of HDLs to build his own circuit by using a
hierarchical and modular approach defined at different levels
of abstraction using the design “top-down methodology”
[52]-[53]. The corresponding design flow is partitioned into
the following four steps:
- System level, where specifications of the circuit are
given;
- Behavior level, that consists in the algorithmic
description of the circuit;
- Register Transfer Level (RTL), where the circuit is
described in terms of its components;
- Physical level, where the circuit is physically described
by taking into account the target hardware
characteristics.
At each level of abstraction, the future integrated circuit
is described in HDL, such as behavioral VHDL or
synthesized VHDL. This last description gives an exact
representation of the operators and variables of the final
circuit.
In order to simulate and validate the digital circuit’s
functionality, various test benches are written and executed.
Moreover, thanks to the advent of analog HDLs such as:
Spectre HDL, VHDL-A, VHDL-AMS [54], it is also
possible to simulate at each level of abstraction the
functionality of the circuit, while taking into account its
analog environment [55]. Another promising approach is the
holistic one that promotes the use of a unique description
language during the whole development procedure [56].
This will be described in more details in the next section.
Fig. 3 presents the hierarchic flow of the top-down design
method and its HDL model environment. Recently, FPGA
manufacturers [6]-[7] have designed software packages that
enable both the simulation and the automatic translation into
hardware of a design. Such software runs inside the Matlab-
Simulink environment for example.
Fig. 3. Top-down design approach.
Simulation results are "bit and cycle accurate". This
means results that are seen in a Simulink simulation exactly
match those produced by hardware implementation. Such an
approach offers an FPGA-based rapid prototyping platform
[57]. It should be mentioned that the concept of automatic
code generation has already been applied with success to
DSP processors [58]. No doubt that this kind of solution will
be more and more utilized in the near future for a rapid
evaluation of new control algorithm performance. However,
this approach is so far still limited to the applications that do
not require the use of complex sequencers. Indeed, control
units are still difficult to achieve with the proposed
Inputs
[3:0
LU
LUT
Chemin
Carry
Path
Bascule
D
D
Flip
-
Flop
Input
carry
Clock
Flip
-
Flop output
Combinatorial
output
Output carry
System
Level
Behavioral
Level
RTL or Synthesi
s
Level
Physical
Level
Simulation
Simulation
Synthesis
Behavioral
HDL
Circuit
Specifications
Simulation
Simulation
Analog
HDL
Test
Bench
Mixed Simulation
Environment
FPGA
ASIC
toolboxes [59]. As a consequence, the resulting hardware
architectures are not area optimized, a fact not acceptable in
an industrial approach.
III.
INTEGRATED SYSTEM MODELING AND DESIGN
Traditionally, mathematical models have been developed
to evaluate the functionality of global engineering systems.
However, the practical development of each part of the
system needs then to be separately addressed. This often
involves the use of other CAD tools and/or different
software platforms, with the design itself being developed in
a different environment. Recent advance in CAD
methodologies / languages has brought the functional
description of design and practical hardware implementation
closer. System level modeling languages (such as Handel-C,
System-C) and Hardware Description Languages (such as
VHDL, Verilog) enable the underpinning mathematical
description and the electronic design implementation to be
simultaneously addressed in a unique environment,
supported by a range of major Computer Aided Engineering
platforms. Synthesis tools can compile such designs into a
variety of target technologies.
A holistic system level approach to the design and
development of an electronic system enables a top-down
design methodology, which begins with modeling an idea at
an abstract level, and proceeds through the iterative steps
necessary to further refine this into a detailed system. A test
environment is developed early in the design cycle. As the
design evolves to completion, the language is able to support
a complex detailed digital system description and the test
environment will check compliance with the original
specification. Concepts are tested before investment is made
in hardware / physical implementation. In terms of holistic
modeling of complex electronic systems, system level
modeling languages offer advantages such as:
Simultaneous consideration of the mathematical aspects
of engineering systems (functional / behavioral
description) and the detailed electronic hardware design,
in the same unique environment, normally supported by a
range of Computer Aided Design platforms.
Ability to handle all levels of abstraction. The system can
be simulated as an overall model during all stages of the
electronic controller design, which can be subsequently
targeted for SoC silicon implementation.
Fast implementation and relatively short time to market.
Easy hardware implementation of Artificial Intelligence.
Versatile reusable models / design modules are
generated, in accordance with modern principles of
design reuse.
Simulation results are valuable to check the behavior of a
model, but on many occasions it is the hardware validation
of a controller that provides significant information before
the decision is taken to invest in an ASIC. The cheapest and
fastest way to validate the design of an optimized digital
controller is via a prototype board containing re-
programmable devices such as FPGAs. This shortens the
time to correct any design problem and it ensures an error
free design before permanent ASIC implementation. The
prototype board can also be used for the hardware testing of
other system components. A modern hardware-in-the-loop
testing approach is also facilitated by this environment,
allowing effective testing of circuit designs. This method
uses a hardware-in-loop-simulator (HILS) that uses the
outputs of the circuit under test as inputs and produces as
outputs the signals that need to be fed to the circuit under
test as inputs. These signals are similar with those given by
the sub-system replaced by the HILS in real-time operation.
More on HILS can be found in [60]-[62].
The DK4 design suite from Celoxica, for example, allows
Handel-C (high level language similar with C) functional
modeling of an electronic system. Handel-C produces an
Electronic Design Interchange Format (EDIF) output when
compiling the design for the hardware target. The Xilinx
placement and routing tools are used to translate the EDIF
format into hardware layout, enabling rapid hardware
implementation onto development boards containing
FPGAs. The compiler can also generate Hardware
Description Language format code such as VHDL, allowing
combinations with other hardware elements in SoC designs.
Portability without design modification of the implemented
system on different PLD/FPGA/ASIC hardware target is
provided using Platform Abstraction Layer (PAL)
Application Programming Interface (API). Thus, Handel-C
can be used as modeling tool and then Xilinx Integrated
Design Environment [6] enables FPGA real-time analysis.
The general benefits of holistic modeling, combined with
the advantages of HDLs and FPGAs, enable novel complex
but fast classical / neural / fuzzy FPGA controllers, with
industrial applications, to be modeled, simulated and
evaluated with efficient use of resource.
IV.
FPGA-B
ASED
C
ONTROLLER
D
ESIGN
R
ULES
FPGA technology allows developing specific hardware
architectures within a flexible programmable environment.
This specific feature of the FPGAs gives designers a new
degree of freedom comparing to microprocessor
implementations, since the hardware architecture of the
control system is not imposed a priori. However, in many
cases, the development of this architecture is rather intuitive
and not adapted to the implementation of more and more
complex algorithms. Thus, in order to benefit from the
advantages of the FPGAs and their powerful CAD tools, the
designer has to follow an efficient design methodology. Such
a methodology rests on three main principles: the control
algorithm refinement, the modularity and the best suitability
between the algorithm to implement and the chosen
hardware architecture. These three concepts are detailed
thereafter.
A. Algorithm refinement
Algorithm refinement is a necessary step when designing
with FPGAs. It is possible to implement floating-point
arithmetic on FPGAs [63], but resources use is not
optimized in this case because of FPGA sea-of-logic-cells
architectures (see Fig. 2). So, in order to reduce cost,
manufacturers require from end-users to design controllers
using fixed-point arithmetic. In this context, cost efficient
architectures must result from a balance between control
performances to respect and complexity of the hardware
architecture to minimise. This leads to formulate two work
directions:
- Simplification of the computation: Many authors,
especially in the early days of FPGAs, when the density of
the chips was limited, proposed smart solutions to avoid
including greedy operators like multipliers in their designs.
Amongst the most commonly used techniques of
simplification, CORDIC can be mentioned, an acronym for
COordinate Rotation DIgital Computer [64]. CORDIC is a
very efficient algorithm, only based on adders/ subtractors
and shifters for computing a wide range of trigonometric,
hyperbolic, linear and logarithmic functions. Another
interesting family of algorithms is the distributed arithmetic
one [65], that can make extensive use of look-up tables
(LUTs), which makes it ideal for implementing DSP
functions in LUT-based FPGAs.
Finally, as explained thereafter, the designer can also
take advantage in remodeling the target algorithm in order to
reduce the number of operations to be implemented.
In order to illustrate these design rules, the authors are
proposing as example a simple function to be implemented.
It consists of an (a,b,c) to (d,q) transformation for three-
phase electrical systems. The coordinate transformation is
used to transform the actual quantities of a three-phase
electrical system (x
a
, x
b
, x
c
) into a dq reference frame that is
rotating at an arbitrary angle θ, while keeping the
instantaneous power equivalent. It gives
( ) ( ) ( )
( ) ( ) ( )
⋅
+−−−−
+−⋅=
c
b
a
q
d
o
x
x
x
x
x
x
3/2sin3/2sinsin
3/2cos3/2coscos
2/12/12/1
3
2
πθπθθ
πθπθθ
(1)
By making the assumption that the studied three-phase
system is balanced (no zero-sequence component), the
transformation can be simplified and expressed as
(
)
(
)
( ) ( )
⋅
−−
−−
⋅=
b
a
q
d
x
x
x
x
θπθ
θπθ
cos3/2cos
sin3/2sin
2
(2)
This first level of simplification allows reducing the
number of operations to be implemented. The former
expression is then converted into a n-bits fixed-point format.
This format must be the result of a compromise between the
required computing accuracy and the available hardware
resources, as it can be seen later on. It gives:
(
)
(
)
( ) ( )
⋅
−
−
=
b
a
q
d
X
X
AA
AA
X
X
θθ
θθ
2221
1211
(3)
where each X n-bit signed fixed-point value is equal to
x
QXx .=
with
1
max
2
−
=
n
x
x
Q
(4)
The scale factor Q
x
, has to be selected with relevance by
the designer so as to avoid overflow errors and in the same
time keeping an acceptable dynamic range. Besides, during
the conversion process, the designer can also simplify the
implemented equations with an adequate choice of scale
factors [34]. In this case, the original square root factor has
disappeared, simplifying once again the computations.
Notice also, the regularity of the operations to be executed,
A
ij
(θ) variables are all sine functions and both dot product
(one per row) have exactly the same computing structure.
This property gives the designer more possibilities of
factorization when building the final architecture (§ IV.C).
- Search for optimized fixed-point formats: As just
mentioned earlier, when developing designs with FPGAs, a
search for the best trade-off between the size of the fixed-
point format of each control variable and the respect of the
control specifications is needed. To this purpose, a
methodology is presented in [66], which is based on the
control system L1 or l1 norms for computing the appropriate
number of bits to represent each quantity of a controller
(coefficients and variables). This methodology is applied
with success to the implementation of a magnetic bearing
FPGA-based control system. In this example, it is also
proved that a delta form realization requires less hardware
than a shift-form realization and provides a closer
approximation to the original analog compensator.
In order to represent all the data values with a sufficient
computation accuracy, Menard et al. propose in [67] a
methodology for an automatic determination of the fixed-
point specification. Firstly, the dynamic range of each data
of the control algorithm is evaluated with the help of the
Interval Arithmetic theory to define the minimal number of
bits needed to represent the data integer part. Then, the
accuracy is evaluated on the basis of an analytical approach.
In the digital signal processing domain, the most common
used criterion for evaluating the fixed-point specification
accuracy is the Signal-to-Quantization-Noise-Ratio (SQNR).
The originality of this approach is that it proposes an
analytical evaluation of the SQNR expression for linear
systems and non-recursive non-linear systems.
B. Design methodology based on reuse modules
For complex designs, modular conception is generally
used to reduce the design cycle. This methodology is based
on hierarchy and regularity concepts. Hierarchy is used to
divide a large or complex design into sub-parts called
modules that are more manageable. Regularity is aimed to
maximize the reuse of already designed modules [68].
With the increasing progress of CAD tools, the
improvement in terms of development time reduction lies
more in the capacity of the designer to know how to classify
and reuse his model module, than in a perfect knowledge of
his CAD tools. Nowadays, the manufacturers and the
designers of circuits even propose to recover in free [69] or
