Journal ArticleDOI
Hardware Efficient Mixed Radix-25/16/9 FFT for LTE Systems
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TLDR
The GHR combines 2-D and 1-D factorization techniques and improves the throughput by a factor of two to four with comparable hardware cost compared with the previous designs, which is nearly two times better than that of previous FFT processors.Abstract:
In this paper, we propose a hardware-efficient mixed generalized high-radix (GHR) reconfigurable fast Fourier transform (FFT) processor for long-term evolution applications. The GHR processor based on radix-25/16/9 uses a 2-D factorization scheme as the high-radix unit and a 1-D factorization method as the system data routing technology. The 2-D factorization scheme is implemented by an enhanced delay element matrix structure, which supports 25-, 16-, 9-, 8-, 5-, 4-, 3-, and 2-point FFTs. Two different designs were implemented. One design (called discrete Fourier transform core) supports 34 different transform sizes from 12 to 1296 points, while the other design (called FFT core) supports five different power-of-two sizes from 128 to 2048 points. The 1-D factorization method is performed by a coprime accessing technology, which accesses the data in parallel without conflict using a RAM. The GHR combines 2-D and 1-D factorization techniques and improves the throughput by a factor of two to four with comparable hardware cost compared with the previous designs. The speed–area ratio of the proposed scheme is nearly two times better than that of previous FFT processors. Application-specified integrated circuit implementation results based on a 0.18- $\mu{\rm m}$ technology are also provided.read more
Citations
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Journal ArticleDOI
VLSI Design and Implementation of Reconfigurable 46-Mode Combined-Radix-Based FFT Hardware Architecture for 3GPP-LTE Applications
TL;DR: This paper presents a reconfigurable fast Fourier transform (FFT) hardware architecture, supporting 46 different FFT sizes defined in 3GPP-LTE applications, and delivers high-quality design results in the aspects of area- and energy-related performance indexes.
Journal ArticleDOI
A High-Flexible Low-Latency Memory-Based FFT Processor for 4G, WLAN, and Future 5G
Shaohan Liu,Dake Liu +1 more
TL;DR: The proposed processor has better-normalized throughput per area unit than the state-of-the-art available designs and is designed as a general IP and can be implemented using a processor synthesizer (application-specific instruction-set processor designer).
Journal ArticleDOI
Low-Power Split-Radix FFT Processors Using Radix-2 Butterfly Units
Zhuo Qian,Martin Margala +1 more
TL;DR: Simulation results show that compared with the conventional radix-2 shared-memory implementations, the proposed design achieves over 20% lower power consumption when computing a 1024-point complex-valued transform.
Journal ArticleDOI
A Memory-Based FFT Processor Design With Generalized Efficient Conflict-Free Address Schemes
TL;DR: The design and implementation of memory-based fast Fourier transform (FFT) processors with generalized efficient, conflict-free address schemes and a method, named high-radix–small-butterfly (HRSB), to decrease the computation cycles and eliminate the complexity of the processing engine are presented.
Journal ArticleDOI
48-Mode Reconfigurable Design of SDF FFT Hardware Architecture Using Radix-3 2 and Radix-2 3 Design Approaches
TL;DR: A reconfigurable (RC) fast Fourier transform (FFT) design in a systematic design scheme that can support up to 2187 FFT-point manipulation and 48 RC modes and supports 32 operating modes defined in 3GPP-LTE standard is proposed.
References
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J.W. Cooley,John W. Tukey +1 more
TL;DR: Good generalized these methods and gave elegant algorithms for which one class of applications is the calculation of Fourier series, applicable to certain problems in which one must multiply an N-vector by an N X N matrix which can be factored into m sparse matrices.
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ASIC Implementation of Soft-Input Soft-Output MIMO Detection Using MMSE Parallel Interference Cancellation
TL;DR: This paper proposes a low-complexity minimum mean-squared error (MMSE) based parallel interference cancellation algorithm, develops a suitable VLSI architecture, and presents a corresponding four-stream 1.5 mm2 detector chip in 90 nm CMOS technology, which is the first ASIC implementation of a SISO detector for iterative MIMO decoding.
Journal ArticleDOI
An introduction to programming the Winograd Fourier transform algorithm (WFTA)
TL;DR: A new approach to the computation of the discrete Fourier transform (DFT) with significantly reduced number of multiplication operations; it does not increase the number of addition operations in many cases.
Journal ArticleDOI
Conflict free memory addressing for dedicated FFT hardware
TL;DR: In this paper, a multibank address assignment for an arbitrary fixed radix fast Fourier transform (FFT) algorithm suitable for high-speed single-chip implementation is developed, which is memory-bank conflict-free to allow simultaneous access to all the data needed for calculation of each of the radix r butterflies as they occur in the algorithm.