Journal ArticleDOI
Implementation of Subthreshold Adiabatic Logic for Ultralow-Power Application
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TLDR
Behavior of adiabatic logic circuits in weak inversion or subthreshold regime is analyzed in depth for the first time in the literature to make great improvement in ultralow-power circuit design.Abstract:
Behavior of adiabatic logic circuits in weak inversion or subthreshold regime is analyzed in depth for the first time in the literature to make great improvement in ultralow-power circuit design. This novel approach is efficacious in low-speed operations where power consumption and longevity are the pivotal concerns instead of performance. The schematic and layout of a 4-bit carry look ahead adder (CLA) has been implemented to show the workability of the proposed logic. The effect of temperature and process parameter variations on subthreshold adiabatic logic-based 4-bit CLA has also been addressed separately. Postlayout simulations show that subthreshold adiabatic units can save significant energy compared with a logically equivalent static CMOS implementation. Results are validated through extensive simulations in 22-nm CMOS technology using CADENCE SPICE Spectra.read more
Citations
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Journal ArticleDOI
TBAL: Tunnel FET-Based Adiabatic Logic for Energy-Efficient, Ultra-Low Voltage IoT Applications
TL;DR: In this paper, a tunnel field effect transistor (TFET)-based adiabatic logic (TBAL) circuit topology has been proposed, evaluated and benchmarked with several device architectures (planar MOSFET, FinFET and TFET) and AL implementations (efficient charge recovery logic, 2N-2N2P, positive feedback adiabiatic logic) operating in the ultra-low voltage ( $0.6~\text{V}$ ) regime.
Journal ArticleDOI
Design and analysis of a logic model for ultra-low power near threshold adiabatic computing
TL;DR: Near threshold adiabatic logic (NTAL) style can perform efficiently using a single sinusoidal power supply which reduces the clock tree management and enhances the energy saving capability.
Journal ArticleDOI
Analysis of Sub-Threshold Adiabatic Logic Model Using Junctionless MOSFET for Low Power Application
TL;DR: In this paper, the authors have presented an analytical modeling of the power dissipation, delay and the power delay product (PDP) of the sub-threshold JL-Inverter structure.
Journal ArticleDOI
An ultra-low power multiplier using multi-valued adiabatic logic in 65 nm CMOS process
TL;DR: The proposed multi-valued adiabatic logic (MVAL) technique for energy-efficient using multiple threshold transistor and switch-level circuit is implemented in 65 nm CMOS process.
Journal ArticleDOI
A balanced power analysis attack resilient adiabatic logic using single charge sharing transistor
Himadri Singh Raghav,Izzet Kale +1 more
TL;DR: A novel PAA resilient adiabatic logic which has a symmetric structure, completely removes NAL from the evaluation phase of the power-clock and exhibits minimal variations in current peaks for gates as well as in an 8-bit Montgomery multiplier is presented.
References
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Book
Sub-threshold Design for Ultra Low-Power Systems
TL;DR: The EKV Model of the MOS Transistor is used as a model for low-voltage circuit design and analog Circuits in Weak Inversion are studied.
Journal ArticleDOI
A 65 nm Sub- $V_{t}$ Microcontroller With Integrated SRAM and Switched Capacitor DC-DC Converter
TL;DR: A 65 nm system-on-a-chip which demonstrates techniques to mitigate variation, enabling sub-threshold operation down to 300 mV, and a switched capacitor DC-DC converter is integrated on-chip, achieving above 75% efficiency.
Journal ArticleDOI
Static noise margin variation for sub-threshold SRAM in 65-nm CMOS
TL;DR: In this article, the authors analyzed SNM for sub-threshold bitcells in a 65-nm process for its dependency on sizing, VDD, temperature, and local and global threshold variation.
Proceedings Article
Robust subthreshold logic for ultra-low power operation
TL;DR: In this paper, variable threshold voltage sub-threshold CMOS (VT-Sub-CMOS) and subthreshold dynamic threshold voltage MOS (Sub-DTMOS) were proposed.
Journal ArticleDOI
Robust subthreshold logic for ultra-low power operation
TL;DR: Two different subth threshold logic families are proposed: 1) variable threshold voltage subthreshold CMOS (VT-Sub-CMOS) and 2) subth thresholds dynamic threshold voltage MOS (Sub-DTMOS) logic.