Journal ArticleDOI
Layout-Driven Post-Placement Techniques for Temperature Reduction and Thermal Gradient Minimization
TLDR
This work proposes two placement techniques that spread cells in hotspots over a larger area, which achieves a larger reduction in both peak temperature and thermal gradient than the baseline method, which enlarges the circuit area uniformly.Abstract:
With the continuing scaling of CMOS technology, on-chip temperature and thermal-induced variations have become a major design concern. To effectively limit the high temperature in a chip equipped with a cost-effective cooling system, thermal specific approaches, besides low power techniques, are necessary at the chip design level. The high temperature in hotspots and large thermal gradients are caused by the high local power density and the nonuniform power dissipation across the chip. With the objective of reducing power density in hotspots, we propose two placement techniques that spread cells in hotspots over a larger area. Increasing the area occupied by the hotspot directly reduces its power density, leading to a reduction in peak temperature and thermal gradient. To minimize the introduced overhead in delay and dynamic power, we maintain the relative positions of the coupling cells in the new layout. We compare the proposed methods in terms of temperature reduction, timing, and area overhead to the baseline method, which enlarges the circuit area uniformly. The experimental results showed that our methods achieve a larger reduction in both peak temperature and thermal gradient than the baseline method. The baseline method, although reducing peak temperature in most cases, has little impact on thermal gradient.read more
Citations
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Proceedings ArticleDOI
Fast Thermal Simulation using SystemC-AMS
TL;DR: This work shows how a standard description language, namely SystemC and its analog and mixed-signal (AMS) extension, can be used to successfully simulate the equivalent thermal network, by achieving accuracy comparable to existing simulators, yet with much better performance.
Proceedings ArticleDOI
ThermPL: Thermal-aware placement based on thermal contribution and locality
TL;DR: This work builds a thermal-aware placer, ThermPL, to abate both on-chip peak temperature and thermal gradient by developing thermal force and padding techniques cooperated with rough legalization in the force-directed global placement.
Journal ArticleDOI
HotSpot Thermal Floorplan Solver Using Conjugate Gradient to Speed Up
Zhonghua Jiang,Ning Xu +1 more
TL;DR: The conjugate gradient method is proposed to use to effectively solve the thermal resistance model in HotSpot thermal floorplan tool, and the iterative method of relative sparse matrix could be applied to other iterative framework algorithms.
References
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Journal ArticleDOI
Negative bias temperature instability: Road to cross in deep submicron silicon semiconductor manufacturing
TL;DR: The negative bias temperature instability (NBTI) commonly observed in p-channel metaloxide-semiconductor field effect transistors when stressed with negative gate voltages at elevated temperatures is discussed in this article.
Journal ArticleDOI
HotSpot: a compact thermal modeling methodology for early-stage VLSI design
TL;DR: The HotSpot compact thermal modeling approach is especially well suited for preregister transfer level (RTL) and presynthesis thermal analysis and is able to provide detailed static and transient temperature information across the die and the package, as it is also computationally efficient.
Proceedings ArticleDOI
Dynamic thermal management for high-performance microprocessors
David Brooks,Margaret Martonosi +1 more
TL;DR: This work investigates dynamic thermal management as a technique to control CPU power dissipation and explores the tradeoffs between several mechanisms for responding to periods of thermal trauma and the effects of hardware and software implementations.
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