Proceedings ArticleDOI
Machine Learning Applications in Physical Design: Recent Results and Directions
Andrew B. Kahng
- pp 68-73
TLDR
Examples applications include removing unnecessary design and modeling margins through correlation mechanisms, achieving faster design convergence through predictors of downstream flow outcomes that comprehend both tools and design instances, and corollaries such as optimizing the usage of design resources licenses and available schedule.Abstract:
In the late-CMOS era, semiconductor and electronics companies face severe product schedule and other competitive pressures. In this context, electronic design automation (EDA) must deliver "design-based equivalent scaling" to help continue essential industry trajectories. A powerful lever for this will be the use of machine learning techniques, both inside and "around" design tools and flows. This paper reviews opportunities for machine learning with a focus on IC physical implementation. Example applications include (1) removing unnecessary design and modeling margins through correlation mechanisms, (2) achieving faster design convergence through predictors of downstream flow outcomes that comprehend both tools and design instances, and (3) corollaries such as optimizing the usage of design resources licenses and available schedule. The paper concludes with open challenges for machine learning in IC physical design.read more
Citations
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Journal ArticleDOI
A graph placement methodology for fast chip design
Azalia Mirhoseini,Anna Goldie,Anna Goldie,Mustafa Yazgan,Joe Wenjie Jiang,Ebrahim M. Songhori,Shen Wang,Young-Joon Lee,Eric Johnson,Omkar Pathak,Azade Nazi,Jiwoo Pak,Andy Tong,Kavya Srinivasa,William Hang,Emre Tuncer,Quoc V. Le,James Laudon,Richard Ho,Roger Carpenter,Jeffrey Dean +20 more
TL;DR: In this article, the authors presented a deep reinforcement learning approach to chip floorplanning, which can automatically generate chip floorplans that are superior or comparable to those produced by humans in all key metrics, including power consumption, performance and chip area.
Journal ArticleDOI
A Deep Reinforcement Learning Approach for Global Routing
TL;DR: This work presents a deep reinforcement learning method for solving the global routing problem in a simulated environment and indicates that the approach can outperform the benchmark method of a sequential A* method, suggesting a promising potential forDeep reinforcement learning for global routing and other routing or path planning problems in general.
Journal ArticleDOI
High-Throughput Calculations for High-Entropy Alloys: A Brief Review
TL;DR: Four different calculation methods that are usually applied to accelerate the development of novel HEA compositions are presented, that is, empirical models, first-principles calculations, calculation of phase diagrams (CALPHAD), and machine learning.
Proceedings ArticleDOI
Using Machine Learning to Predict Path-Based Slack from Graph-Based Timing Analysis
TL;DR: A machine learning model is proposed, based on bigrams of path stages, to predict expensive PBA results from relatively inexpensive GBA results, which has the potential to substantially reduce pessimism while retaining the lower turnaround time of GBA analysis.
Journal ArticleDOI
Accelerating Chip Design With Machine Learning
Brucek Khailany,Haoxing Ren,Steve Dai,Saad Godil,Ben Keller,Robert M. Kirby,Alicia Klinefelter,Rangharajan Venkatesan,Yanqing Zhang,Bryan Catanzaro,William J. Dally +10 more
TL;DR: This work reviews recent research applying techniques such as deep convolutional neural networks and graph-based neural networks in the areas of automatic design space exploration, power analysis, VLSI physical design, and analog design.
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