Journal ArticleDOI
Mapping Statistical Process Variations Toward Circuit Performance Variability: An Analytical Modeling Approach
Yu Cao,Lawrence T. Clark +1 more
TLDR
An analytical gate delay model is developed by integrating short-channel effects and the Alpha-power law-based timing model, which accurately predicts both nominal delay and delay variability over a wide range of power supply conditions including subthreshold and strong- inversion regions.Abstract:
An analytical gate delay model is developed by integrating short-channel effects and the Alpha-power law-based timing model. As verified with an industrial 90-nm technology, this analytical approach accurately predicts both nominal delay and delay variability over a wide range of power supply conditions including subthreshold and strong- inversion regions. Excellent model scalability enables efficient mapping between process variations and delay variability at the gate level. Based on this model, the impact of various physical effects on delay variability has been identified. While the variation of effective channel length is the leading source for delay variability at the current 90-nm node, delay variability is actually more sensitive to the variation of threshold voltage, especially in the subthreshold region. Furthermore, the limitation of low-power design techniques is investigated in the presence of process variations, particularly dual Vth and L biasing. These techniques become less effective at low VDD due to excessive delay variability.read more
Citations
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Journal ArticleDOI
Understanding the Effect of Process Variations on the Delay of Static and Domino Logic
TL;DR: Analysis shows that domino logic circuits suffer from a doubled variability as compared to the static CMOS logic style, which adds to the well-known speed degradation due to the current contention associated with the keeper transistor.
Journal ArticleDOI
Interests and Limitations of Technology Scaling for Subthreshold Logic
TL;DR: The interests and limitations of technology scaling for subthreshold logic are investigated from 0.25 mum to 32 nm nodes, which shows scaling to 90/65 nm nodes is shown to be highly desirable for medium-throughput applications due to great dynamic energy reduction.
Proceedings ArticleDOI
Impact of process variations on multicore performance symmetry
TL;DR: The potential magnitude ofMulti-core architectures introduce a new granularity at which process variations may occur, yielding asymmetry among cores that were designed---and that software expects---to be symmetric in performance, and this paper explores the potential magnitude.
Journal ArticleDOI
Technologies for Ultradynamic Voltage Scaling
Anantha P. Chandrakasan,Denis C. Daly,D.F. Finchelstein,Joyce Kwong,Yogesh Ramadass,Mahmut E. Sinangil,Vivienne Sze,Naveen Verma +7 more
TL;DR: Voltage-scalable circuits such as logic cells, SRAMs, ADCs,ADCs, and dc-dc converters are presented, using these circuits as building blocks for two different applications.
Journal ArticleDOI
A Unified Framework for Multimodal Submodular Integrated Circuits Trojan Detection
TL;DR: A unified formal framework for integrated circuits (ICs) Trojan detection that can simultaneously employ multiple noninvasive side-channel measurement types (modalities) and a new submodular formulation of the problem objective function is devised.
References
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Book
Response Surface Methodology: Process and Product Optimization Using Designed Experiments
TL;DR: Using a practical approach, this book discusses two-level factorial and fractional factorial designs, several aspects of empirical modeling with regression techniques, focusing on response surface methodology, mixture experiments and robust design techniques.
Journal ArticleDOI
Alpha-power law MOSFET model and its applications to CMOS inverter delay and other formulas
Takayasu Sakurai,A.R. Newton +1 more
TL;DR: In this paper, an alpha-power-law MOS model that includes the carrier velocity saturation effect, which becomes prominent in short-channel MOSFETs, is introduced and closed-form expressions for the delay, short-circuit power, and transition voltage of CMOS inverters are derived.
Journal ArticleDOI
Impact of die-to-die and within-die parameter fluctuations on the maximum clock frequency distribution for gigascale integration
TL;DR: In this paper, a model describing the maximum clock frequency distribution of a microprocessor is derived and compared with wafer sort data for a recent 0.25-/spl mu/m microprocessor.
Journal ArticleDOI
Adaptive body bias for reducing impacts of die-to-die and within-die parameter variations on microprocessor frequency and leakage
James W. Tschanz,James Kao,Siva G. Narendra,Rajendran Nair,Dimitri A. Antoniadis,Anantha P. Chandrakasan,Vivek De +6 more
TL;DR: Bidirectional adaptive body bias (ABB) is used to compensate for die-to-die parameter variations by applying an optimum pMOS and nMOS body bias voltage to each die which maximizes the die frequency subject to a power constraint as mentioned in this paper.
Die-to-Die and Within-Die Parameter Variations on Microprocessor Frequency and Leakage
James W. Tschanz,James Kao,Siva G. Narendra,Rajendran Nair,Dimitri A. Antoniadis,Anantha P. Chandrakasan,Vivek De +6 more
TL;DR: Measurements on a 150 nm CMOS test chip show that on-chip bidirectional adaptive body biasing compensates effectively for die-to-die parameter variation to meet both frequency and leakage requirements.
Related Papers (5)
Alpha-power law MOSFET model and its applications to CMOS inverter delay and other formulas
Takayasu Sakurai,A.R. Newton +1 more
Mapping statistical process variations toward circuit performance variability: an analytical modeling approach
Yu Cao,Lawrence T. Clark +1 more