Journal ArticleDOI
New Generation of Predictive Technology Model for Sub-45 nm Early Design Exploration
TLDR
In this article, a new generation of predictive technology model (PTM) is developed to predict the characteristics of nanoscale CMOS, including process variations and correlations among model parameters.Abstract:
A predictive MOSFET model is critical for early circuit design research. To accurately predict the characteristics of nanoscale CMOS, emerging physical effects, such as process variations and correlations among model parameters, must be included. In this paper, a new generation of predictive technology model (PTM) is developed to accomplish this goal. Based on physical models and early-stage silicon data, the PTM of bulk CMOS is successfully generated for 130- to 32-nm technology nodes, with an Leff of as low as 13 nm. The accuracy of PTM predictions is comprehensively verified: The error of I on is below 10% for both n-channel MOS and p-channel MOS. By tuning only ten primary parameters, the PTM can be easily customized to cover a wide range of process uncertainties. Furthermore, the new PTM correctly captures process sensitivities in the nanometer regime, particularly the interactions among Leff, Vth, mobility, and saturation velocity. A website has been established for the release of PTM: http://www.eas.asu.edu/~ptmread more
Citations
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Journal ArticleDOI
Device Requirements for Optical Interconnects to Silicon Chips
TL;DR: The current performance and future demands of interconnects to and on silicon chips are examined and the requirements for optoelectronic and optical devices are project if optics is to solve the major problems of interConnects for future high-performance silicon chips.
Journal ArticleDOI
A Compact SPICE Model for Carbon-Nanotube Field-Effect Transistors Including Nonidealities and Its Application—Part I: Model of the Intrinsic Channel Region
Jie Deng,Hon-Sum Philip Wong +1 more
TL;DR: In this paper, a circuit-compatible compact model for the intrinsic channel region of the MOSFET-like single-walled carbon-nanotube field effect transistors (CNFETs) is presented.
Journal ArticleDOI
A Compact SPICE Model for Carbon-Nanotube Field-Effect Transistors Including Nonidealities and Its Application—Part II: Full Device Model and Circuit Performance Benchmarking
Jie Deng,Hon-Sum Philip Wong +1 more
TL;DR: In this paper, a universal circuit-compatible CNFET model including the practical device nonidealities is implemented with HSPICE, including elastic scattering in the channel region, resistive source/drain (S/D), Schottky-barrier resistance, and parasitic gate capacitances.
Proceedings ArticleDOI
Ambit: in-memory accelerator for bulk bitwise operations using commodity DRAM technology
Vivek Seshadri,Donghyuk Lee,Thomas Mullins,Hasan Hassan,Amirali Boroumand,Jeremie S. Kim,Michael Kozuch,Onur Mutlu,Phillip B. Gibbons,Todd C. Mowry +9 more
TL;DR: Ambit is proposed, an Accelerator-in-Memory for bulk bitwise operations that largely exploits existing DRAM structure, and hence incurs low cost on top of commodity DRAM designs (1% of DRAM chip area).
Journal ArticleDOI
A 160 mV Robust Schmitt Trigger Based Subthreshold SRAM
TL;DR: A novel Schmitt trigger (ST) based differential 10-transistor SRAM (static random access memory) bitcell suitable for subthreshold operation and does not require any architectural changes from the present 6T architecture is proposed.
References
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Proceedings ArticleDOI
New paradigm of predictive MOSFET and interconnect modeling for early circuit simulation
TL;DR: A new paradigm of predictive MOSFET and interconnect modeling is introduced to specifically address SPICE compatible parameters for future technology generations and comparisons with published data and 2D simulations are used to verify this predictive technology model.
Journal ArticleDOI
Predictive technology model for nano-CMOS design exploration
TL;DR: A new generation of predictive technology model (PTM) is developed, covering emerging physical effects and alternative structures, based on physical models and early stage silicon data, and correctly captures process sensitivities in the nanometer regime.
Book ChapterDOI
Models of Process Variations in Device and Interconnect
TL;DR: This chapter contains sections titled: Introduction: Sources of Variation Overview: Statistical Descriptions Survey of Process Variations Methods to Characterize and Address Variation Application of Methods to Interconnect Impact Analysis and Conclusion.
Proceedings ArticleDOI
A 130 nm generation logic technology featuring 70 nm transistors, dual Vt transistors and 6 layers of Cu interconnects
Sunit Tyagi,Mohsen Alavi,Robert M. Bigwood,T. Bramblett,J. Brandenburg,W. Chen,B. Crew,Makarem A. Hussein,P. Jacob,C. Kenyon,C. Lo,B. McIntyre,Z. Ma,Peter K. Moon,P. Nguyen,L. Rumaner,R. Schweinfurth,Swaminathan Sivakumar,M. Stettler,Scott E. Thompson,B. Tufts,J. Xu,Simon Yang,M. Bohr +23 more
TL;DR: In this paper, a leading edge 130 nm generation logic technology with 6 layers of dual damascene Cu interconnects is reported, where dual Vt transistors are employed with 1.5 nm thick gate oxide and operating at 1.3 V.
Proceedings ArticleDOI
High speed 45nm gate length CMOSFETs integrated into a 90nm bulk technology incorporating strain engineering
Victor Chan,Rajesh Rengarajan,Nivo Rovedo,Wei Jin,Terence B. Hook,Phung T. Nguyen,Jia Chen,E.J. Nowak,X. Chen,D. Lea,Ashima B. Chakravarti,Victor Ku,See-Hun Yang,An L. Steegen,Christopher V. Baiocco,Padraic Shafer,Hung Ng,Shih-Fen Huang,C. Wann +18 more
TL;DR: In this article, a leading edge 90 nm logic bulk foundry with 45 nm gate length devices, incorporating strain engineering, is described, which enable high performance devices, which are amongst the best reported to date short channel effect control down to 35 nm.
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