Journal ArticleDOI
Modeling and analysis of substrate coupling in integrated circuits
Ranjit Gharpurey,Robert G. Meyer +1 more
TLDR
In this article, a fast and accurate simulator for characterizing the effects of substrate coupling on integrated-circuit performance is presented, which uses the electrostatic Green function of the substrate medium and the fast Fourier transform algorithm.Abstract:
This paper describes a fast and accurate simulator for characterizing the effects of substrate coupling on integrated-circuit performance. The technique uses the electrostatic Green function of the substrate medium and the fast Fourier transform algorithm. It is demonstrated that this technique is suitable for optimization of layout for minimization of substrate coupling. Analysis of substrate coupling in different types of substrates and the utility of guard rings in different types of substrates is also discussed. Experimental verification of the models is presented.read more
Citations
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Journal ArticleDOI
Analysis, design, and optimization of spiral inductors and transformers for Si RF ICs
Ali M. Niknejad,Robert G. Meyer +1 more
TL;DR: In this article, the authors used classic circuit analysis and network analysis techniques to derive two-port parameters from spiral inductors and transformers and applied them to traditional square and polygon inductors, as well as multilayer metal structures and coupled inductors.
Journal ArticleDOI
Computer-aided design of analog and mixed-signal integrated circuits
Georges Gielen,Rob A. Rutenbar +1 more
TL;DR: This survey presents an overview of recent advances in the state of the art for computer-aided design (CAD) tools for analog and mixed-signal integrated circuits (ICs) and outlines progress on the various design problems involved.
Journal Article
Experimental Results and Modeling Techniques for Substrate Noise in Mixed-Signal Integrated Circuits
TL;DR: In this article, the effects of switching transients in digital MOS circuits that perturb analog circuits integrated on the same die by means of coupling through the substrate were observed. And the authors showed that in such cases the substrate noise is highly dependent on layout geometry.
Book
ESD in silicon integrated circuits
TL;DR: ESD Phenomena and Test Methods The Physics of ESD Protection Circuit Elements Requirements and Synthesis of ESD Protection Circuits Design and Layout Requirements Analysis and Case Studies Modelling of ESC in Integrated Circuits Effects of Processing and Packaging.
Journal ArticleDOI
Substrate crosstalk reduction using SOI technology
TL;DR: In this paper, the authors analyzed both by simulations and measurements the substrate crosstalk performances of various Silicon-On-Insulator (SOI) technologies, and compared them to those of normal bulk CMOS process.
References
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Journal ArticleDOI
FastCap: a multipole accelerated 3-D capacitance extraction program
K. Nabors,Jacob K. White +1 more
TL;DR: Performance comparisons on integrated circuit bus crossing problems show that for problems with as few as 12 conductors the multipole accelerated boundary element method can be nearly 500 times faster than Gaussian-elimination-based algorithms, and five to ten times slower than the iterative method alone, depending on required accuracy.
Journal ArticleDOI
Experimental results and modeling techniques for substrate noise in mixed-signal integrated circuits
TL;DR: In this paper, the effects of switching transients in digital MOS circuits that perturb analog circuits integrated on the same die by means of coupling through the substrate were observed. But the authors did not consider the effect of the layout geometry of the substrate.
Journal Article
Experimental Results and Modeling Techniques for Substrate Noise in Mixed-Signal Integrated Circuits
TL;DR: In this article, the effects of switching transients in digital MOS circuits that perturb analog circuits integrated on the same die by means of coupling through the substrate were observed. And the authors showed that in such cases the substrate noise is highly dependent on layout geometry.