1652 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 25, NO. 9, SEPTEMBER 2006
Optimal Synthesis of Multiple Output Boolean
Functions Using a Set of Quantum Gates
by Symbolic Reachability Analysis
William N. N. Hung, Xiaoyu Song, Guowu Yang, Jin Yang, and Marek Perkowski
Abstract—This paper proposes an approach to optimally syn-
thesize quantum circuits by symbolic reachability analysis, where
the primary inputs and outputs are basis binary and the inter-
nal signals can be nonbinary in a multiple-valued domain. The
authors present an optimal synthesis method to minimize quan-
tum cost and some speedup methods with nonoptimal quantum
cost. The methods here are applicable to small reversible func-
tions. Unlike previous works that use permutative reversible gates,
a lower level library that includes nonpermutative quantum gates
is used here. The proposed approach obtains the minimum cost
quantum circuits for Miller gate, half adder, and full adder, which
are better than previous results. This cost is minimum for any
circuit using the set of quantum gates in this paper, where the con-
trol qubit of 2-qubit gates is always basis binary. In addition, the
minimum quantum cost in the same manner for Fredkin, Peres,
and Toffoli gates is proven. The method can also find the best
conversion from an irreversible function to a reversible circuit as a
byproduct of the generality of its formulation, thus synthesizing in
principle arbitrary multi-output Boolean functions with quantum
gate library. This paper constitutes the first successful experience
of applying formal methods and satisfiability to quantum logic
synthesis.
Index Terms—Formal verification, logic synthesis, model check-
ing, quantum computing, reversible logic, satisfiability.
I. INTRODUCTION
R
EVERSIBLE logic [1] plays an important role in the
synthesis of quantum computing circuits [2], [3]. The
synthesis of reversible logic circuits using elementary quantum
gates [4], [5] is different from classical (nonreversible) logic
synthesis. There are some works [6]–[9] on reversible logic
synthesis using basic reversible gates (Toffoli, Fredkin [10], or
Feynman gates). However, these reversible logic gates have dif-
ferent quantum implementation costs (e.g., the cost of Feynman
is lower than Toffoli). Therefore, finding the smallest number
of gates to synthesize a reversible circuit does not necessarily
result in quantum implementation with the lowest cost (in terms
of quantum gates).
Manuscript received November 8, 2004; revised February 22, 2005 and
June 8, 2005. This paper was recommended by Associate Editor J. H. Kukula.
W. N. N. Hung is with Synplicity Inc., Sunnyvale, CA 94086 USA (e-mail:
william_hung@alumni.utexas.net).
X. Song, G. Yang, and M. Perkowski are with Portland State University,
Portland, OR 97207 USA.
J. Yang is with Strategic CAD Labs, Intel Corporation, Hillsboro, OR 97124
USA.
Digital Object Identifier 10.1109/TCAD.2005.858352
In this paper, we focus on synthesizing reversible circuits
using quantum primitives with the lowest total cost using a
library of basic 2-qubit quantum gates, which will be described
in Section III. Our synthesis method can also be modified to
use other libraries of gates. We chose a library of basic 2-qubit
quantum gates in this paper as they allow us to better evaluate
the quantum implementation costs. The circuits we synthesized
include common reversible gates that can next be used at higher
levels of logic synthesis. Our approach can also be used as an
equivalent of “technology mapping” for quantum circuits.
We reduce the quantum logic synthesis problem to multiple-
valued logic synthesis; this reduction simplifies the search
space and reduces the algorithm complexity. We formulate the
above quantum logic synthesis task via symbolic reachability
analysis [11], [12]. We used satisfiability-based model checking
to solve the problem, but other decision methods or combinato-
rial optimization techniques can be similarly applied here. Our
method not only guarantees to find a quantum implementation
(for reversible circuits) but also guarantees the lowest quantum
cost in the synthesized result (for the set of circuits where
the control qubit of our 2-qubit gates is always basis binary).
We also introduce an automated way of adding ancilla qubits
and finding their appropriate constant values in the synthesis
process. Thus, even irreversible circuits can be converted to
reversible circuits that in turn are synthesized by our method.
In contrast to previous works, which either use permutative
reversible gates to design permutative circuits or universal
quantum gates to design quantum circuits, we use a subset of
quantum gates to design permutative circuits.
II. B
ACKGROUND
Given a function f,wesayf is reversible if and only if there
exists a function g such that x = g(f(x)) for all x in the domain
of f. The corresponding function g (as described above) is usu-
ally referred to as f
−1
.Givenn Boolean inputs, any multiple-
output Boolean function on such n Boolean inputs must have
exactly n Boolean outputs so that it is reversible [2]. We use
n × n to denote a reversible function with n Boolean inputs
and n Boolean outputs. Given an n × n reversible function f,
there are 2
n
input rows and 2
n
output rows in the truth table of
f. The output rows must be a permutation of the input rows in
the truth table of f.
In quantum computing [2], the fundamental information unit
is a qubit. The state of a qubit is a superposition of 0 and 1
0278-0070/$20.00 © 2006 IEEE
HUNG et al.: OPTIMAL SYNTHESIS OF MULTIPLE OUTPUT BOOLEAN FUNCTIONS USING QUANTUM GATES 1653
states, also denoted as |0 and |1, respectively. The qubit state
q can be represented by
q = α|0 + β|1
where α and β are both complex numbers and |α|
2
+ |β|
2
=1.
The classical state of binary 0 corresponds to the case where
α =1and β =0. Similarly, the classical state of binary 1 cor-
responds to α =0and β =1. We refer to them as basis binary
0 and basis binary 1, respectively. All other combinations of α
and β are not basis binary. The quantum state of a single qubit
is usually denoted by the vector
α
β
.
Given the state of each qubit, the overall quantum state is a
Kronecker product of the states of each qubit. Take two qubits
for example
u
0
u
1
⊗
v
0
v
1
=
u
0
v
0
v
1
u
1
v
0
v
1
=
u
0
v
0
u
0
v
1
u
1
v
0
u
1
v
1
. (1)
Notice that if the individual qubits are basis binary, then the
Kronecker product is simply an enumeration of all the possible
binary values (truth table) of its qubits. If we can use the
quantum state of multiple qubits to determine the individual
state of each qubit (such as the above case), we call it a
separable state. There are some cases where the quantum state
cannot be separated into individual states of each qubit, i.e., we
cannot describe (mathematically) the state of each qubit but
we can describe the quantum state of all the qubits combined.
We call such states entangled states. This idea of entangled
state is called quantum entanglement, and it originated from
the Einstein–Podolsky–Rosen paradox [13].
The effect of quantum gates on a quantum state can be
described as vector operations, where the quantum gates are
represented by unitary matrices. A unitary matrix is a n × n
complex matrix M with the property
M × M
+
= M
+
× M = I
where I is the identity matrix and M
+
is the conjugate trans-
pose (also known as the Hermitian adjoint) of M.
Given an n-qubit quantum gate G, we call G a permutative
quantum gate if and only if the outputs of G are all basis binary
when its inputs are all basis binary, i.e., G is a permutative
quantum gate if and only if G implements an n × n Boolean
reversible function (when its inputs are basis binary).
A generalized 2-qubit controlled U gate [5] is shown in
Fig. 1. Its unitary matrix is
10 0 0
01 0 0
00u
00
u
01
00u
10
u
11
Fig. 1. Controlled-U gate.
where the four entries in the right bottom also form a (single
qubit) unitary matrix U by itself
U =
u
00
u
01
u
10
u
11
.
It has been shown [4], [5] that permutative quantum logic
circuits can be constructed using elementary quantum,
XOR,
controlled-V , controlled-V
+
,orNOT gates, as shown in Fig. 2.
The
NOT gate is also called an inverter. Its unitary matrix is
M
NOT
=
01
10
.
Quantum
XOR gates are also called Feynman gates or
controlled-
NOT (CNOT) gates. The controlled-V gate’s data
output is the same as its data input (B) when its control input
(A) value is 0 (FALSE). When its control value is 1 (TRUE),
the data output becomes V (input) [2]
V =
1+i
2
1 −i
−i 1
,V
+
=
1 − i
2
1 i
i 1
.
Similar rules apply to the controlled-V
+
gate, except that its
data output becomes V
+
(input), where V
+
is the Hermitian of
V , i.e.,
1+i
2
1 −i
−i 1
×
1 − i
2
1 i
i 1
=
10
01
.
The quantum
XOR (controlled-NOT), controlled-V , and
controlled-V
+
are all special cases of the generalized
controlled-U gate, where the matrix U corresponds to M
NOT
,
V , and V
+
, respectively.
According to [2], the values V and V
+
are constructed
such that they are the square root of
NOT (i.e., inverter gate):
V × V = V
+
× V
+
= M
NOT
. Hence, if the signal V (input)
is passed through another controlled-V gate with its control
value also equal to 1 (TRUE), the output of the second gate
becomes the
NOT of the input.
The quantum
XOR, controlled-V , and controlled-V
+
gates
are 2 × 2 gates. They are also called 2-qubit gates. Similarly, the
NOT gate (inverter) is a 1-qubit gate. For quantum implementa-
tion, the cost of 2-qubit gates far exceeds the cost of 1-qubit
gates. Hence, in a first approximation, the quantum cost of
1-qubit gates is usually ignored in the presence of 2-qubit
implementations [5], [14].
In this paper, we adopt the quantum gate cost evalu-
ation introduced in [4]. According to the method in [4],
each of the 2-qubit gates (quantum
XOR, controlled-V ,
controlled-V
+
) has a quantum implementation cost of 1.
In addition, when both quantum
XOR and controlled-V (or
controlled-V
+
) are operating on the same two qubits in a
1654 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 25, NO. 9, SEPTEMBER 2006
Fig. 2. Elementary quantum logic gates.
Fig. 3. Merged 2-qubit gates.
symmetric pattern (shown in Fig. 3), their total cost is consid-
ered as 1 as well. A more accurate cost function can be created
for a particular quantum technology such as nuclear magnetic
resonance (NMR) [15], but for simplicity and comparison to
previous work we will use here the cost function from [4].
Given a reversible function, the quantum logic synthesis task
considered in this paper is to synthesize the function using
the above elementary quantum logic gates with the minimum
cost. Various heuristic methods have been applied to find low-
cost quantum implementations (using the elementary gates)
for the functionality of the Fredkin [4], Toffoli [16], and
Peres [17] gates. Yet, nobody has been able to prove that they
have the lowest quantum cost implementation (based on the
cost evaluation criteria given above).
We can perform the above quantum logic synthesis task
through reachability analysis. Symbolic reachability analysis is
a well-known technique in formal verification [11]. Its basic
idea is to find all the reachable states of a finite state machine
(FSM). Using symbolic representation, we can check if an
invariant (property) is true for all reachable states. This tech-
nique is used in invariant checking [11], where the state space
is traversed exhaustively against an invariant. Since the state
space tends to be large for practical systems, recent symbolic
reachability analysis techniques use various methods, such
as binary decision diagram (BDD) [18], [19] or satisfiability
(SAT), to avoid enumerating every system state while preserv-
ing the completeness of the reachability analysis. We use state-
of-the-art SAT-based bounded model checking [12] to check
invariants. If the invariant is false, it can automatically generate
a counter-example. We can find the shortest counter-example
in this way by starting with a zero bound and gradually incre-
menting the bound. If the invariant is true and given enough
time, this method can also check that the bound is sufficiently
large and establish the proof. SAT-based model checking has
been successfully deployed in the industry [20]–[22].
III. S
YMBOLIC FORMULATION
We consider each “quantum wire” of the quantum circuit as
a superposition of |1 and |0, denoted as 1 and 0, respectively.
We are interested in synthesizing quantum circuits with basis
binary inputs (1 and 0). The values of these signals are modified
after passing through elementary gates (Fig. 2). There are six
possible output values when we apply binary (1 and 0) inputs
to one of those elementary gates: 0, 1, V
0
, V
1
, V
+
0
, V
+
1
, where
V
0
represents V (input) when the input is 0, and similarly for
V
1
, V
+
0
, V
+
1
, i.e.,
V
0
=
1+i
2
1 −i
−i 1
×
1
0
=
1+i
2
1
−i
V
1
=
1+i
2
1 −i
−i 1
×
0
1
=
1+i
2
−i
1
V
+
0
=
1 − i
2
1 i
i 1
×
1
0
=
1 − i
2
1
i
V
+
1
=
1 − i
2
1 i
i 1
×
0
1
=
1 − i
2
i
1
.
These six possible values are used as input values to gates
in subsequent stages. We want to synthesize our circuit
such that the “control” input of controlled-
NOT (quantum
XOR), controlled-V , or controlled-V
+
is always basis binary
(0s and 1s), i.e., their input values cannot be V
0
or V
1
,etc.
We impose the above restriction because a nonbinary value
at the control input of the controlled-
NOT, controlled-V ,or
controlled-V
+
gate can generate an entangled quantum state.
For example, if we have V
0
at both control and data inputs
of the controlled-V gate, the unitary matrix multiplied by the
Kronecker product (of the inputs) becomes
10 0 0
01 0 0
00
1+i
2
1−i
2
00
1−i
2
1+i
2
×
0.5i
0.5
0.5
−0.5i
=
0.5i
0.5
0
0.5 − 0.5i
.
The vector result cannot be separated into two individual qubit
states using (1). The u
1
u
0
entry from (1) is 0, which requires
u
1
= u
0
=0. It contradicts with the other entries of the vector.
This is an entangled quantum state. Similar scenarios exist for
controlled-V
+
. The controlled-NOT also has similar examples
[23]. For the rest of this paper, we focus on synthesizing quan-
tum circuits using our set of quantum gates (
NOT, controlled-
NOT, controlled-V , and controlled-V
+
), where the control
input of the 2-qubit gates is always basis binary. However, the
same approach can be used to synthesize circuits using other
libraries of quantum gates as long as it can be reduced to a
multiple-valued logic problem.
HUNG et al.: OPTIMAL SYNTHESIS OF MULTIPLE OUTPUT BOOLEAN FUNCTIONS USING QUANTUM GATES 1655
Based on the unitary matrices in Section II, we can see that
if the input of the
NOT gate is not basis binary, namely V
0
, V
1
,
V
+
0
,orV
+
1
, its corresponding output is V
1
, V
0
, V
+
1
,orV
+
0
,
respectively. Given a basis binary 1 on the control input of the
controlled-
NOT gate, the data input and the data output exhibit
the same property (above) as the
NOT gate. Also, as shown in
Section II, given the six possible values (0, 1, V
0
, V
1
, V
+
0
or
V
+
1
) at the data input of the controlled-V or controlled-V
+
,
their corresponding data output has the same set of six possible
values. Hence, the input/output of every quantum gate in the
circuit can be represented using the above six values.
If we look at the complex matrix representation of V
0
, V
1
,
V
+
0
, and V
+
1
, we can deduce that V
0
= V
+
1
V
0
=
1+i
2
1
−i
=
0.5+0.5i
0.5 − 0.5i
V
+
1
=
1 − i
2
i
1
=
0.5+0.5i
0.5 − 0.5i
and V
1
= V
+
0
V
1
=
1+i
2
−i
1
=
0.5 − 0.5i
0.5+0.5i
V
+
0
=
1 − i
2
1
i
=
0.5 − 0.5i
0.5+0.5i
.
Thus, it suffices to represent signals in the circuit using four
values:0,1,V
0
, V
1
. In this way, we reduce the problem of
quantum circuit synthesis (which would normally use unitary
matrices and Hilbert space to represent signals) to a simpler
synthesis problem in mixed binary/quaternary algebra. This
is a general approach to efficiently synthesize a subclass of
quantum circuits. It can be applied to gates other than the
2-qubit gates introduced above.
Theorem 1: For any deterministic quantum circuit (with n
qubits, n>0) that produces basis binary outputs for basis
binary inputs, its unitary matrix is canonical, i.e., there is only
one unitary matrix that represents the function of this circuit.
This is a permutation matrix.
Proof: We prove the theorem in four steps. Step 1): There
are 2
n
! distinct n × n binary reversible logic functions. Step 2):
When all n qubits are basis binary, their Kronecker product has
one entry equal to 1 while all the other entries are equal to 0.
Step 3): Each row or column of the unitary matrix should have
only one entry equal to 1 while all the other entries are equal
to 0. Step 4): The unitary matrix must be unique under the above
circumstances.
Step 1) The function of this quantum circuit is a binary
reversible logic function. The output entries in the
truth table are permutations of the input entries
for this function. The truth table has 2
n
rows, i.e.,
2
n
distinct binary input entries (and corresponding
output entries). Since the output entries are permu-
tations of the 2
n
input entries, there are 2
n
! ways to
permute them. Hence, there are 2
n
! distinct n × n
binary reversible logic functions.
Step 2) The Kronecker product of n qubits is
α
1
β
1
⊗···⊗
α
n
β
n
=
α
1
α
2
,...,α
n−1
α
n
α
1
α
2
,...,α
n−1
β
n
.
.
.
β
1
β
2
,...,β
n−1
β
n
.
For each qubit, αβ have only two choices (10 or 01)
to be basis binary. There are 2
n
distinct ways for all
n qubits to be basis binary. Under this circumstance,
the above Kronecker product is an enumeration of
the truth table patterns for α and β of each qubit.
Hence, there is one entry in the Kronecker product
equal to 1 while all the other entries are equal to 0.
Step 3) Let U be a unitary matrix of the n-qubit circuit.
There are 2
n
rows and 2
n
columns in U .LetP and
Q be the Kronecker product of the input and output
for this circuit, respectively. We have
U × P = Q. (2)
According to Step 2), the vector P has one entry
equal to 1 and all the other entries are 0. Similarly,
the vector Q has one entry equal to 1 and all the
other entries are 0. We use u
ij
to denote the value of
matrix U in the ith row and jth column, and p
i
and
q
i
to denote the value of vector P and Q in the ith
row, respectively.
Given 0 ≤ i ≤ 2
n
, suppose all the entries in the ith
row of U are 0, then q
i
will be 0 for all possible
values of P due to (2). This is a contradiction
because Q has 2
n
rows and 2
n
distinct values, so
q
i
must be 1 for one of those cases. Hence, any row
of U cannot be all zeros.
Furthermore, suppose there are more than one en-
try that is nonzero (say columns u
ij
and u
ik
are
nonzero), then we can have two distinct patterns
of P , one with p
j
=1and the other with p
k
=1,
both being able to produce a nonzero q
i
.Again,this
is a contradiction because we can only have one
possibility for q
i
to be nonzero. Hence, every row
of U must have exactly one nonzero entry. In order
to produce a corresponding 1 in the vector Q,the
nonzero entry in U must be 1.
Lastly, suppose we have u
ij
=1and u
kj
=1, both
in the jth column. We can pick a valuation of P
with p
j
=1. The corresponding vector Q will have
q
i
=1 and q
k
=1. This is again a contradiction
since only one row of vector Q can be nonzero.
Thus, every column of U must have exactly one
nonzero entry (which must be 1).
Step 4) There are 2
n
! possibilities for U to satisfy the prop-
erty in Step 3), which is exactly the number of
distinct permutations. Hence, to each permutation
corresponds a unique unitary matrix U. This com-
pletes the Proof of Theorem 1.
The importance of the above theorem is that once we have
specified the basis binary input/output behavior of the quantum
1656 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 25, NO. 9, SEPTEMBER 2006
circuit, there is only one unitary matrix that can satisfy the
specification (because it is canonical). Hence, the functional
behavior of the synthesized quantum circuit, under nonbinary
(complex number) input/outputs, would be deterministic, even
though they were not in the original specification. This idea
is especially important for the synthesis of binary reversible
functions (Toffoli, Fredkin, etc.) using quantum gates. It suf-
fices to specify the basis binary input/output behavior of the
reversible function, and the synthesized quantum circuit would
have identical behavior as those of classical quantum circuits
for all quantum values.
Suppose we intend to synthesize an n × n reversible function
R specified by its truth table with n input columns, n output
columns, and 2
n
rows corresponding to n output patterns using
the 2-qubit quantum gates [Fig. 2(b)–(d)] described above. The
synthesized result should be a cascade of L stages. Each stage
consists of one of the above quantum gates. Since the function
applies to n qubits and the quantum gates at each stage are
1-qubit or 2-qubit gates, the synthesized result should indicate
to which qubits the gates are connected. For each stage i,we
use g
i
to represent the gate selection variable [Fig. 2(b)–(d)],
and we use A
i
and B
i
to indicate the two qubits that the
gate is connected to, i.e., A
i
,B
i
∈{1,...,n}. As a naming
convention, we refer to the qubit indicated by A
i
[the upper
qubit in Fig. 2(b)–(d)] as the control qubit, and we refer to the
qubit indicated by B
i
[the lower qubit in Fig. 2(b)–(d)] as the
data qubit. Since the two qubits must be different, we have
A
i
= B
i
. (3)
We denote the inputs of stage i as
U
i
, where
U
i
=
u
1i
u
2i
, ···,u
ni
. Each qubit (u
qi
, q =1,...,n) of the stage i
can have four possible values (0, 1, V
0
, V
1
). The output of stage
i is denoted by
U
i+1
, i.e.,
u
q (i+1)
=
u
A
i
i
⊕
Q
u
qi
, (q = B
i
)∧(g = Fig. 1(b))
V (u
qi
), (q = B
i
)∧(g = Fig. 1(c))∧u
A
i
i
V
+
(u
qi
), (q = B
i
)∧(g = Fig. 1(d))∧u
A
i
i
u
qi
, otherwise.
Note that we use ⊕
Q
to denote the quantum XOR operation.
Due to our restriction on the control input, the values V
0
and
V
1
cannot be applied to the control input of controlled-NOT,
controlled-V , or controlled-V
+
gates. We create a Boolean
signal E
i
to represent whether the gate has been erroneously
configured (misconfigured) with the V
0
or V
1
values in the
current (ith) synthesis stage or any previous synthesis stages. At
the initial stage, there is no misconfiguration, and we initialize
by setting
E
0
=0.
As we move to subsequent stages, the E
i+1
value (in stage
i +1) is 1 if either of the following two cases is true.
1) E
i
(in the previous stage) is already 1.
2) The value of the control qubit u
A
i
i
is not binary (where
A
i
is the control qubit).
Fig. 4. L-2Syn problem.
Thus
E
i+1
= E
i
∨ (u
A
i
i
∈{0, 1}) .
So far, g
i
had only three possible values [Fig. 2(b)–(d)]. To
better reflect the quantum implementation cost, let us use a
different gate selection variable G
i
with seven possible values.
G
i
has all the three possible values of g
i
, with four additional
values to reflect the quantum
XOR gate merged with controlled-
V and controlled-V
+
gates (Fig. 3). We define the synthesis
function S as
(
U
i+1
,E
i+1
)=S(G
i
,A
i
,B
i
,
U
i
,E
i
). (4)
Definition 1 (L-2Syn): The quantum logic synthesis problem
for the reversible function R using 2-qubit gates as a cascade
of L stages is to find a set of satisfying values to G
i
, A
i
, B
i
(where A
i
= B
i
and i =0, 1,...,L− 1) such that E
0
= E
L
=
0 and
U
L
= R(
U
0
) for all possible Boolean input values of
U
0
. Mathematically speaking, a solution to the L-2Syn problem
exists if and only if
∃G
0
∃A
0
∃B
0
,...,∃G
L−1
∃A
L−1
∃B
L−1
·
∀
U
0
∈{0, 1}
n
·(E
0
= E
L
=0)∧
U
L
= R(
U
0
)
∧
L−1
i=0
A
i
= B
i
(5)
where G
0
A
0
B
0
,G
1
A
1
B
1
,...,G
L−1
A
L−1
B
L−1
form a solu-
tion to the L-2Syn problem.
Fig. 4 illustrates the L-2Syn problem. Notice that we are
performing n × n reversible logic synthesis here. E
0
is not
an input constant to the reversible logic circuit because all the
reversible gates use only qubits 1,...,n.TheE
i
(i =0,...,n)
Boolean values are used to keep track of prohibited logic values,
they are not a part of the reversible circuit.
Definition 2 (min-2Syn): The minimum length quantum
logic synthesis problem for the reversible function R using
2-qubit gates (quantum
XOR, controlled-V , controlled-V
+
,or
their merged versions) is to solve L-2Syn with the smallest
possible number L.
Theorem 2: For any reversible function R that does not
require inverters in its quantum implementation, finding its
quantum logic implementation with the minimum cost is equiv-
alent to solving the min-2Syn for R.
Proof: The min-2Syn solution consists of the smallest
possible L stages where each stage has a quantum cost of 1.
Thus, the minimum quantum cost is L.
