Journal ArticleDOI
PFD with improved average gain and minimal blind zone combined with lock-in detection for fast settling PLLs
H. K. Ravi,Jayanta Mukherjee +1 more
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TLDR
In this article, two phase frequency detector (PFD) architectures and a PFD with lock-in detection (LID) are proposed that are designed using the new techniques for selectively resetting the outputs to achieve improved average gain with a lower blind zone.About:
This article is published in Microelectronics Journal.The article was published on 2021-10-01. It has received 6 citations till now. The article focuses on the topics: Phase-locked loop & Phase frequency detector.read more
Citations
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Journal ArticleDOI
A Novel Blind Zone Free, Low Power Phase Frequency Detector for Fast Locking of Charge Pump Phase Locked Loops
TL;DR: In this paper , a phase frequency detector (PFD) based on edge detector is proposed to achieve zero blind zone by eliminating the reset pulse beyond the dead zone region, which reduces the phase noise.
Journal ArticleDOI
Dead zone-less low power phase frequency detector, independent of duty cycle variations for charge pump phase locked loop
Journal ArticleDOI
Low power 10T phase and frequency detector for high frequency phase locked loop
TL;DR: In this paper , the authors proposed a 10T phase and frequency detector (PFD) for low-power phase-locked loop (PLL), which employs Gate Diffusion Input (GDI) logic based D-flip flop and the pass transistor logic in the reset path to reduce power consumption.
Journal ArticleDOI
Blind Zone-Less Phase Frequency Detector for a Low-Power Phase-Locked Loop Architecture
Journal ArticleDOI
An integrated 0.0625–4 GHz quadrature-output fractional-N frequency synthesizer for software-defined radios
TL;DR: In this article , a 0.0625-4 GHz fractional-N frequency synthesizer with quadrature phase output for software-defined radios (SDRs) is presented.
References
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Journal ArticleDOI
Increasing processor performance by implementing deeper pipelines
Eric Sprangle,Doug Carmean +1 more
TL;DR: It is shown that in the same process technology, designing deeper pipelines can increase the processor frequency by 100%, which, when combined with larger on-chip caches can yield performance improvements of 35% to 90% over a Pentium® 4 like processor.
Proceedings Article
Fast frequency acquisition phase-frequency detectors for GSa/s phase-locked loops
TL;DR: In this paper, two techniques for phase-frequency detectors (PFDs) with higher operating frequencies (periods of less than 8x the delay of a fan-out-4 inverter (FO-4)) and faster frequency acquisition are described.
Journal ArticleDOI
Analysis of charge-pump phase-locked loops
TL;DR: In this article, an exact analysis for third-order charge-pump phase-locked loops using state equations is presented, and the effect of the loop parameters and the reference frequency on the loop phase margin and stability is analyzed.
Journal ArticleDOI
A 6.3-9-GHz CMOS fast settling PLL for MB-OFDM UWB applications
TL;DR: In this paper, a CMOS phase-locked loop (PLL) which synthesizes frequencies between 6.336 and 8.976 GHz in steps of 528 MHz and settles in approximately 150 ns is presented.
Journal ArticleDOI
Phase Frequency Detector With Minimal Blind Zone for Fast Frequency Acquisition
TL;DR: A technique is proposed that removes the blind zone caused by the precharge time of the internal nodes in latch-based PFDs and achieves a small blind zone close to the limit imposed by process-voltage-temperature variations.