Proceedings ArticleDOI
Polysilicon interconnections (FEOL): Fabrication and characterization
Ajay Agarwal,Ramana Murthy,Vincent Lee,Gautham Viswanadam +3 more
- pp 317-320
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TLDR
In this article, the authors present a vias-first process to realize vertical interconnects that is fully FEOL compatible, where the vias are filled by doped polysilicon and wafers with such pre-fabricated vias can be used as the starting wafer for any CMOS device processing.Abstract:
Three dimensional silicon integration technologies are gaining considerable attention as the traditional CMOS scaling becoming more challenging and less beneficial. The advanced packaging solutions based on thin silicon carrier are being developed to interconnect integrated circuits and other devices at high densities. A key enabling technology element of the silicon carrier is Through Silicon Via (TSV), which can provide vertical interconnects in stacked ICs. In this paper, we present vias-first process to realize vertical interconnects that is fully FEOL compatible. The vias are filled by doped polysilicon and wafers with such pre-fabricated vias can be used as the starting wafers for any CMOS device processing. The process details and their characterization are elaborated along with the physical and electrical analysis of such vias.read more
Citations
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Journal ArticleDOI
3-D Integration and Through-Silicon Vias in MEMS and Microsensors
TL;DR: The 3-D integration is also an enabling technology for hetero-integration of microelectromechanical systems (MEMS)/microsensors with different technologies, such as CMOS and optoelectronics as discussed by the authors.
Journal ArticleDOI
Microsystems using three-dimensional integration and TSV technologies: Fundamentals and applications
TL;DR: The fundamental fabrication technologies of 3D integration are introduced, the recent progresses of MEMS and microsystems using 3D Integration and TSV technologies are reviewed, and the conclusions are made and the future trends are discussed.
Journal ArticleDOI
Power Distribution in TSV-Based 3-D Processor-Memory Stacks
S. M. Satheesh,Emre Salman +1 more
TL;DR: It is demonstrated that the area overhead of a 3-D power distribution network with via-first TSVs is approximately 9% as compared to less than 2% in via-middle and via-last technologies.
Patent
Semiconductor structure having a through substrate via (TSV) and method for forming
TL;DR: In this article, a structure having a substrate includes an opening in the substrate having depth from a top surface of the substrate to a bottom surface of a substrate, where conductive material fills the opening.
Journal ArticleDOI
Fabrication and electrical characterization of high aspect ratio poly-silicon filled through-silicon vias
TL;DR: In this paper, the fabrication and electrical characterization of poly-Si filled through-silicon vias, which were etched in a 180 µm thin silicon device wafer, were bonded to a handle wafer by plasma activated oxide-tosilicon bonding.
References
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Journal ArticleDOI
Fabrication and characterization of robust through-silicon vias for silicon-carrier applications
P.S. Andry,Cornelia K. Tsang,B. C. Webb,Edmund J. Sprogis,Steven L. Wright,B. Dang,Dennis G. Manzer +6 more
TL;DR: The evolution in both TSV design and process flow that has led to TSV technology which produces vias with resistances on the order of 10-20 mΩ and yields on the orders of 99.99% at wafer level in a research laboratory environment is discussed.
Journal ArticleDOI
3D-LSI technology for image sensor
TL;DR: In this article, the authors describe the process and structure of the chip size package (CSP), developed on the basis of current and advanced 3D-LSI technologies, to be used in CMOS image sensors.
Proceedings ArticleDOI
Via First Technology Development Based on High Aspect Ratio Trenches Filled with Doped Polysilicon
David Henry,X. Baillin,V. Lapras,M.H. Vaudaine,J.M. Quemper,N. Sillon,Brendan Dunne,Caroline Hernandez,E. Vigier-Blanc +8 more
TL;DR: In this paper, a new via-first technology for TSV which is compatible with CMOS high temperature steps is presented, which is based on filling high aspect ratio trenches with doped polysilicon and thinning the silicon after active device bonding onto a wafer carrier.
Journal ArticleDOI
Integration of High Aspect Ratio Tapered Silicon Via for Silicon Carrier Fabrication
N. Ranganathan,Liao Ebin,Linn Linn,Wen-Sheng Lee,O.K. Navas,Vaidyanathan Kripesh,N. Balasubramanian +6 more
TL;DR: In this article, a detailed overview of silicon carrier-based packaging for 3D system in packaging application is provided, where various critical process modules that play a vital role in the integration and fabrication of silicon carriers with high aspect ratio tapered through-silicon interconnections have been explained and discussed with experimental data.