Pre-layout module wise decap allocation for noise suppression and accurate delay estimation of SoC
01 May 2016-pp 1-6
TL;DR: Estimation of decoupling capacitance at sub-module stage based on their power dissipation and proper allocation of decap at the pre-layout level is addressed and satisfactory suppression of noise is found at the cost of negligible increase in power and delay.
Abstract: This paper addresses estimation of decoupling capacitance (decap) at sub-module stage based on their power dissipation and proper allocation of decap at the pre-layout level. Decap being in between power and ground distribution networks acts as local charge storage and effectively reduces rapid transients in the supply drop. Therefore, present trends in VLSI design are inclined towards the placement of decoupling capacitors for system on chip (SoC) design. But, early prediction and allocation of decaps at appropriate locations in the pre-layout circuit can only provide a better scope in optimizing power, noise and delay effects for the circuit. The novelty of our work lies in exhaustive module wise estimation of di/dt drop for the complete circuit, followed by an algorithmic estimation and appropriate allocation of decaps with an effort to keep power, delay and noise performance to its best. We choose Double DES as example crypto-core for our test circuits as this is quite complex in nature and are also used as custom cores in many SoC applications. We investigate the change in power, noise and delay parameters with and without the decap allocation for multi-core circuits at the pre-layout stage and find satisfactory suppression of noise at the cost of negligible increase in power and delay. By using our approach, average peak noise and maximum peak noise can be suppressed approximately by 22.7% and 32.23% respectively at the pre-layout stage comparing with the previous works. This early prediction helps in more accurate Computer Aided Design (CAD) implementation at the layout stage.
Citations
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01 Jan 2002
TL;DR: This paper presents frequency-domain sensitivity-analysis based decoupling capacitance placement for reducing the voltage variation in the power distribution network and experimental results on circuits extracted from layout are presented to validate the simulation and optimization techniques.
Abstract: In this paper, we present simulation techniques to estimate the worst-case voltage variation using a RC model for the power distribution network. Pattern independent maximum envelope currents are used as a periodic input for performing the frequency-domain steady-state simulation of the linear RC circuit to evaluate the worst-case instantaneous voltage drop for the RC power distribution networks. The proposed technique unlike existing techniques, is guaranteed to give the maximum voltage drop at nodes in the RC power distribution network. We present experimental results to compare the frequency-domain and time-domain simulation techniques for estimating the maximum instantaneous voltage drop. We also present frequency-domain sensitivity-analysis based decoupling capacitance placement for reducing the voltage variation in the power distribution network. Experimental results on circuits extracted from layout are presented to validate the simulation and optimization techniques.
22 citations
04 Jul 2019
TL;DR: This work rectifies on-chip crosstalk noise at gate-level with special consideration to the worst case crosStalk effect when forbidden data streams ‘101’ and ‘010’ are transmitted by the adjacent wires.
Abstract: Deep sub-micron technology design presents great challenges to design engineers since the digital noise present on-chip becomes a crucial metric in handling signal integrity issues. On-chip noise contributes detrimentally to information being carried by a circuit net and also causes delay uncertainty. As the wires are placed close to each other, coupling capacitances (\(C_c\)) become significant leading to non-critical paths gaining critical path status. To address on-chip crosstalk noise problem, most design approaches involve layout optimization or post-layout corrections. This includes shielding wires from each other by placement of guard wires between two signal nets, a practice most common in PCB designs. However, with continued scaling, a lot of circuit nets would require noise corrections and layout optimization approach would cause area and timing issues. This work rectifies on-chip crosstalk noise at gate-level with special consideration to the worst case crosstalk effect when forbidden data streams ‘101’ and ‘010’ are transmitted by the adjacent wires. The paper presents a novel crosstalk reduction circuit that reduces crosstalk noise by 86%. By using the proposed circuit, the timing uncertainty was reduced to below 9%, with area and power penalties below 40%. All the simulations are carried out using silicon extracted spice models.
References
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Book•
01 Jun 1998
2,624 citations
"Pre-layout module wise decap alloca..." refers methods in this paper
...In this paper, we explore the problem of on chip decap deployment through module wise analysis as well as power, peak supply noise and delay analysis at pre-layout level for crypto-SoC architecture [14, 15]....
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IBM1
TL;DR: A new design methodology to analyzethe on-chip power supply noise for high-performance microprocessors based on an integrated package-level and chip-level power bus model, and a simulated switching circuit model for each functional block offers the most complete and accurate analysis of Vdd distribution.
Abstract: This paper describes a new design methodology to analyzethe on-chip power supply noise for high-performance microprocessors.Based on an integrated package-level andchip-level power bus model, and a simulated switching circuitmodel for each functional block, this methodology offersthe most complete and accurate analysis of Vdd distributionfor the entire chip. The analysis results not only providedesigners with the inductive ΔI noise and the resistive IRdrop data at the same time, but also allow designers to easilyidentify the hot spots on the chip and ΔV across the chip.Global and local optimization such as buffer sizing, powerbus sizing, and on-chip decoupling capacitor placement canthen be conducted to maximize the circuit performance andminimize the noise.
325 citations
"Pre-layout module wise decap alloca..." refers background or methods in this paper
...The most commonly used techniques are topology optimization [8], wire sizing [9], on chip voltage regulation [10], and decoupling capacitance (decap) deployment [2], [11] to relieve peak power-supply noise....
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...In the recent era, many research works [2]–[7] have focused on the power supply noise analysis and power distribution network (PDN) optimization....
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TL;DR: Three generations of Alpha microprocessors have been designed using a proven custom design methodology that facilitates high clock speed, and the chip organization for each generation was carefully chosen to meet critical paths.
Abstract: Three generations of Alpha microprocessors have been designed using a proven custom design methodology. The performance of these microprocessors was optimized by focusing on high-frequency design. The Alpha instruction set architecture facilitates high clock speed, and the chip organization for each generation was carefully chosen to meet critical paths. Digital has developed six generations of CMOS technology optimized for high-frequency design. Complex circuit styles were used extensively to meet aggressive cycle time goals. CAD tools were developed internally to support these designs. This paper discusses some of the technologies that have enabled Alpha microprocessors to achieve high performance.
317 citations
TL;DR: This paper presents a new technique for analyzing a power grid using macromodels that are created for a set of partitions of the grid, and shows that even for a 60 million-node power grid, the approach allows for an efficient analysis, whereas previous approaches have been unable to handle power grids of such size.
Abstract: Careful design and verification of the power distribution network of a chip are of critical importance to ensure its reliable performance. With the increasing number of transistors on a chip, the size of the power network has grown so large as to make the verification task very challenging. The available computational power and memory resources impose limitations on the size of networks that can be analyzed using currently known techniques. Many of today's designs have power networks that are too large to be analyzed in the traditional way as flat networks. In this paper, we propose a hierarchical analysis technique to overcome the aforesaid capacity limitation. We present a new technique for analyzing a power grid using macromodels that are created for a set of partitions of the grid. Efficient numerical techniques for the computation and sparsification of the port admittance matrices of the macromodels are presented. A novel sparsification technique using a 0-1 integer linear programming formulation is proposed to achieve superior sparsification for a specified error. The run-time and memory efficiency of the proposed method are illustrated on industrial designs. It is shown that even for a 60 million-node power grid, our approach allows for an efficient analysis, whereas previous approaches have been unable to handle power grids of such size.
284 citations
01 Jun 2000
TL;DR: A new technique for analyzing a power grid using macromodels that are created for a set of partitions of the grid, and a novel sparsification technique using a 0-1 integer linear programming formulation is proposed to achieve superiorSparsification for a specified error.
Abstract: Careful design and verification of the power distribution network of a chip are of critical importance to ensure its reliable performance. With the increasing number of transistors on a chip, the size of the power network has grown so large as to make the verification task very challenging. The available computational power and memory resources impose limitations on the size of networks that can be analyzed using currently known techniques. Many of today's designs have power networks that are too large to be analyzed in the traditional way as flat networks. In this paper, we propose a hierarchical analysis technique to overcome the aforesaid capacity limitation. We present a new technique for analyzing a power grid using macromodels that are created for a set of partitions of the grid. Efficient numerical techniques for the computation and sparsification of the port admittance matrices of the macromodels are presented. A novel sparsification technique using a 0-1 integer linear programming formulation is proposed to achieve superior sparsification for a specified error. The run-time and memory efficiency of the proposed method are illustrated through the analysis of case studies of several multi-million node power grids, extracted from real microprocessor and DSP designs.
204 citations