Proceedings ArticleDOI
Progress and challenges in VLSI placement research
Igor L. Markov,Jin Hu,Myung-Chul Kim +2 more
- pp 275-282
Reads0
Chats0
TLDR
The history of placement research, the progress leading up to the state of the art, and outstanding challenges are surveyed.Abstract:
Given the significance of placement in IC physical design, extensive research studies performed over the last 50 years addressed numerous aspects of global and detailed placement. The objectives and the constraints dominant in placement have been revised many times over, and continue to evolve. Additionally, the increasing scale of placement instances affects the algorithms of choice for high-performance tools. We survey the history of placement research, the progress achieved up to now, and outstanding challenges.read more
Citations
More filters
Proceedings ArticleDOI
Hybrid Heuristic Algorithm for VLSI Placement
TL;DR: The authors suggest an approach based on a bee algorithms at the first level for searching a diversifying and parallel genetic algorithm at the second level to provide a depth search in the vicinity of the points to solve the placement problem of VLSI fragments placement.
Journal ArticleDOI
Detailed Placement for Dedicated LUT-Level FPGA Interconnect
TL;DR: This work proposes an efficient ILP-based detailed placer which moves a carefully selected subset of LUTs from their original positions, so that connections of the user circuit can be appropriately aligned with the direct connection of the FPGA, reducing the circuit’s critical path delay.
Proceedings ArticleDOI
Physical Layout after Half a Century: From Back-Board Ordering to Multi-Dimensional Placement and Beyond
Ilgweon Kang,Chung-Kuan Cheng +1 more
TL;DR: Dr. Goto's career in VLSI designs sets an exemplar role model for young engineers and his contributions are used as a thread to describe his personal view of physical layout from early back-board ordering to recent multi-dimensional placement and the future.
Proceedings ArticleDOI
Wot the L: Analysis of Real versus Random Placed Nets, and Implications for Steiner Tree Heuristics
TL;DR: It is shown that a pointset attribute which is called L-ness highlights the difference between real placements and random placements of net pins, and an improved lookup table-based RSMT cost estimator is presented that includes an L-nesses parameter.
Universidade federal de santa catarina programa de pós-graduação em engenharia de automação e sistemas
TL;DR: This work presents the development of a computational model for study of the energetic behavior of a brushless motor and a frequency inverter used to drive it, using the technique of representation by Bond Graphs to create a fully graphical representation for the model.
References
More filters
Proceedings ArticleDOI
A Linear-Time Heuristic for Improving Network Partitions
TL;DR: An iterative mincut heuristic for partitioning networks is presented whose worst case computation time, per pass, grows linearly with the size of the network.
Book
Monotone operators in Banach space and nonlinear partial differential equations
TL;DR: PDE examples by type linear problems as mentioned in this paper, including nonlinear stationary problems, nonlinear evolution problems, and nonlinear Cauchy problems, can be found in this paper.
Book ChapterDOI
VPR: A new packing, placement and routing tool for FPGA research
Vaughn Betz,Jonathan Rose +1 more
TL;DR: In terms of minimizing routing area, VPR outperforms all published FPGA place and route tools to which the authors can compare and presents placement and routing results on a new set of circuits more typical of today's industrial designs.
Book
Algorithms for VLSI Physical Design Automation
TL;DR: This book is a core reference for graduate students and CAD professionals and presents a balance of theory and practice in a intuitive manner.