Proceedings ArticleDOI
Progress and challenges in VLSI placement research
Igor L. Markov,Jin Hu,Myung-Chul Kim +2 more
- pp 275-282
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TLDR
The history of placement research, the progress leading up to the state of the art, and outstanding challenges are surveyed.Abstract:
Given the significance of placement in IC physical design, extensive research studies performed over the last 50 years addressed numerous aspects of global and detailed placement. The objectives and the constraints dominant in placement have been revised many times over, and continue to evolve. Additionally, the increasing scale of placement instances affects the algorithms of choice for high-performance tools. We survey the history of placement research, the progress achieved up to now, and outstanding challenges.read more
Citations
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Modern microprocessor built from complementary carbon nanotube transistors
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A graph placement methodology for fast chip design
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TL;DR: In this article, the authors presented a deep reinforcement learning approach to chip floorplanning, which can automatically generate chip floorplans that are superior or comparable to those produced by humans in all key metrics, including power consumption, performance and chip area.
References
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Proceedings ArticleDOI
Clock-Tree Aware Placement Based on Dynamic Clock-Tree Building
TL;DR: A novel dynamic clock-tree building technique integrated into placement for zero-skew design is proposed, which combines a pre-designed clock- tree with the force-directed placement procedure to navigate the register placement for minimizing the clock network.
Proceedings ArticleDOI
Porosity aware buffered steiner tree construction
TL;DR: This work addresses the problem of finding porosity-aware buffering solutions by constructing a "smart Steiner tree" to pass to van Ginneken's topology-based algorithm, and shows that significant improvements on timing closure are obtained when this approach is integrated into a physical synthesis system.
Proceedings ArticleDOI
Perimeter-degree: a priori metric for directly measuring and homogenizing interconnection complexity in multilevel placement
TL;DR: An accurate metric (perimeter-degree) for measuring interconnection complexity and effective use of it for controlling congestion in a multilevel framework is described and empirical evidence for the effectiveness of perimeter-degree in effectively identifying congested regions even before they are formed is provided.