Journal ArticleDOI
Radiation effects in SOI technologies
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TLDR
In this paper, the authors review the total dose, single-event effects, and dose rate hardness of silicon-on-insulator (SOI) devices and use body ties to reduce bipolar amplification.Abstract:
Silicon-on-insulator (SOI) technologies have been developed for radiation-hardened applications for many years and are rapidly becoming a main-stream commercial technology. The authors review the total dose, single-event effects, and dose rate hardness of SOI devices. The total dose response of SOI devices is more complex than for bulk-silicon devices due to the buried oxide. Radiation-induced trapped charge in the buried oxide can increase the leakage current of partially depleted transistors and decrease the threshold voltage and increase the leakage current of fully depleted transistors. Process techniques that reduce the net amount of radiation-induced positive charge trapped in the buried oxide and device design techniques that mitigate the effects of trapped charge in the buried oxide have been developed to harden SOI devices to bulk-silicon device levels. The sensitive volume for charge collection in SOI technologies is much smaller than for bulk-silicon devices potentially making SOI devices much harder to single-event upset (SEU). However, bipolar amplification caused by floating body effects can significantly reduce the SEU hardness of SOI devices. Body ties are used to reduce floating body effects and improve SEU hardness. SOI ICs are completely immune to classic four-layer p-n-p-n single-event latchup; however, floating body effects make SOI ICs susceptible to single-event snapback (single transistor latch). The sensitive volume for dose rate effects is typically two orders of magnitude lower for SOI devices than for bulk-silicon devices. By using body ties to reduce bipolar amplification, much higher dose rate upset levels can be achieved for SOI devices than for bulk-silicon devices.read more
Citations
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References
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Journal ArticleDOI
Silicon on insulator material technology
TL;DR: In this article, a silicon on insulator material technology based on wafer bonding is described, in which a heat treatment induces an in-depth microslicing of one of the two bonded wafers previously implanted with hydrogen.
Journal ArticleDOI
Threshold voltage of thin-film Silicon-on-insulator (SOI) MOSFET's
Hyung-Kyu Lim,Jerry G. Fossum +1 more
TL;DR: In this article, the charge coupling between the front and back gates of thin-film silicon-on-insulator (SOI) MOSFETs is analyzed, and closed-form expressions for the threshold voltage under all possible steady-state conditions are derived.
Book
Electrical Characterization of Silicon-on-Insulator Materials and Devices
Sorin Cristoloveanu,Sheng S. Li +1 more
Abstract: 1. Introduction. 2. Methods of Forming SOI Wafers. 3. SOI Devices. 4. Wafer Screening Techniques. 5. Transport Measurements. 6. SUS Capacitor Based Characterization Techniques. 7. Diode Measurements. 8. Transistor Characteristics. 9. Transistor Based Characterization Techniques. 10. Monitoring the Transistor Degradation. Index.
Journal ArticleDOI
Satellite Anomalies from Galactic Cosmic Rays
TL;DR: In this article, the authors investigated the effect of cosmic rays on the capacitance of transistors to the turn-on voltage of the base-emitter capacitance and determined the number of sensitive transistors.
Journal ArticleDOI
Analysis and control of floating-body bipolar effects in fully depleted submicrometer SOI MOSFET's
J.-Y. Choi,Jerry G. Fossum +1 more
TL;DR: In this paper, the authors analyzed the floating body effects triggered by impact ionization in fully depleted submicrometer silicon-on-insulator (SOI) MOSFETs based on two-dimensional device simulations.