Proceedings ArticleDOI
Reducing power in high-performance microprocessors
Vivek Tiwari,Deo Singh,Suresh Rajgopal,Gaurav G. Mehta,Rakesh Patel,Franklin M. Baez +5 more
- pp 732-737
TLDR
The main trends that are driving the increased focus on design for low power are described and areas that need increased research focus in the future are also pointed out.Abstract:
Power consumption has become one of the biggest challenges in high-performance microprocessor design. The rapid increase in the complexity and speed of each new CPU generation is outstripping the benefits of voltage reduction and feature size scaling. Designers are thus continuously challenged to come up with innovative ways to reduce power, while trying to meet all the other constraints imposed on the design. This paper presents an overview of the issues related to power consumption in the context of Intel CPUs. The main trends that are driving the increased focus on design for low power are described. System and benchmarking issues, and sources of power consumption in a high-performance CPU are briefly described. Techniques that have been tried on real designs in the past are described. The role of CAD tools and their limitations in this domain will also be discussed. In addition, areas that need increased research focus in the future are also pointed out.read more
Citations
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Dissertation
Formal methods for intellectual property composition across synchronization domains
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Patent
Instruction scheduling approach to improve processor performance
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Proceedings ArticleDOI
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Journal ArticleDOI
Design of Low Power Adaptive Pulse TriggeredFlip-Flop Using Modified Clock Gating Schemeat 90nm Technology
TL;DR: Simulation results indicate that the proposed PTFF features best power delay product performance and excels conventional designs in performance metrics such as average power consumption, minimum D to Q delay, and power-delay-product.
References
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Journal ArticleDOI
Minimizing power consumption in digital CMOS circuits
TL;DR: An approach is presented for minimizing power consumption for digital systems implemented in CMOS which involves optimization at all levels of the design and has been applied to the design of a chipset for a portable multimedia terminal that supports pen input, speech I/O and full-motion video.
Journal ArticleDOI
Instruction level power analysis and optimization of software
TL;DR: This paper describes an alternative, measurement based instruction level power analysis approach that provides an accurate and practical way of quantifying the power cost of soft-ware and guides the development of general tools and techniques for low power software.
Proceedings ArticleDOI
Technology Decomposition and Mapping Targeting Low Power Dissipation
TL;DR: This paper generates a NAND decomposition of an optimized Boolean network such that the sum of average switching rates for all nodes in the network is minimum and performs a power efficient technology mapping that finds an optimal power-delay trade-off value for given timing constraints.
Proceedings ArticleDOI
Technology Mapping for Low Power
TL;DR: This paper focuses on the problem of mapping a technology independent circuit to a technology specific one, using gates from a given library, with power as the optimization metric, and observes that a significant variation in the power consumption is possible just by varying the choice of gates.
Proceedings ArticleDOI
Technology mapping for lower power
TL;DR: This paper focuses on the problem of mapping a technology independent circuit to a technology specific one, using gates from a given library, with power as the optimization metric, and observes that a significant variation in the power consumption is possible just by varying the choice of gates.