Patent
Si-Ge CMOS semiconductor device
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TLDR
In this article, a SiGe layer and the intrinsic surface region are provided epitaxially, the thickness of the siGe layer being so small that the lattice constants in the epitaxial layers do not or substantially not differ from those in the substrate in a plane parallel to the surface, while a sufficient diffusion-inhibiting effect is retained.Abstract:
To obtain a high mobility and a suitable threshold voltage in MOS transistors with channel dimensions in the deep sub-micron range, it is desirable to bury a strongly doped layer (or ground plane) in the channel region below a weakly doped intrinsic surface region, a few tens of nm below the surface. It was found, however, that degradation of the mobility can occur particularly in n-channel transistors owing to diffusion of boron atoms from the strongly doped layer to the surface, for example during the formation of the gate oxide. To prevent this degradation, a thin layer 11 of Si 1−x Ge x inhibiting boron diffusion is provided between the strongly doped layer 10 and the intrinsic surface region 7 , for example with x=0.3. The SiGe layer and the intrinsic surface region may be provided epitaxially, the thickness of the SiGe layer being so small that the lattice constants in the epitaxial layers do not or substantially not differ from those in the substrate 1 in a plane parallel to the surface, while a sufficient diffusion-inhibiting effect is retained. Since SiGe has a diffusion-accelerating rather than decelerating effect on n-type dopants, the ground plane of a p-channel transistor in a CMOS embodiment is doped with As or Sb because of the low diffusion rate of these elements in pure silicon.read more
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References
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