Signal Integrity and Power Integrity Methodology for Robust Analysis of On-the-Board System for High Speed Serial Links

TLDR: A Generic Flow for complete On-the- Board System Level Simulation to simulate and analyze the Reliability and Robustness of any PHY, in context of high speed data transmission.

Abstract: Integrated System Level Simulations of high speed serial links are necessary for the channel reliability and robustness. Increasing data rates and sharp transition time require high bandwidth systems. System level simulation are required to optimize channel design keeping cost of implementation at moderate or low level while meeting system level channel Bit Error Rate requirement for high bandwidth systems. The parameters which influence the channel and it's interconnect environment are primarily governed by signal integrity and power integrity requirements. In this paper, System Level Robustness Analysis of High Speed Serial Links is demonstrated with external environment considerations taken into account. A strong correlation between measured and simulated results is shown. A generic methodology for high speed serial links is presented with complete analysis of package, board, termination, Signal Quality inrush Droop/Drop (SQiDD), decoupling network etc. I. INTRODUCTION In Semiconductor industry due to tool limitations package analysis, board analysis, mixed signal simulations are performed separately. The complete channel performance is cumulative effect of whole interconnect environment consisting of transceiver, bond wire, package substrate, board, media/cable and termination environment. 'On-the- Board System' means die, package and board integrated together, to form a complete system. There is always a trade off between the various entities which form part of channel environment. In high speed transceivers, Signal Integrity (SI) and Power Integrity (PI) are the most important factors for the designers to keep in the mind while designing a system, as it affects the reliability of transmission at high data rates. This paper presents a Generic Flow for complete On-the- Board System Level Simulation to simulate and analyze the Reliability and Robustness of any PHY ( with example of USB 2.0 PHY), in context of high speed data transmission. Three advantages of SI and PI Analysis are: 1) This analysis is useful to perceive the behavior of whole system at simulation level accurately. 2) This can be used to ensure the Robustness and Reliability of a channel for the targeted bit error rate. 3) It will help the designers to modify the system before it is fabricated. Thus it will reduce product cost and minimize silicon iterations. II. SIGNAL AND POWER INTEGRITY AT SYSTEM LEVEL Signal Integrity means to preserve the signal as it propagates through the media between the transmitter and the receiver (i.e. without distortion in its amplitude shape and jitter performance). At higher speeds, board traces and package signal nets behave like transmission lines. In Serial Links (at system level), there are many types of losses/reflections that may cause distortion in signal quality e.g. reflection loss, insertion loss, coupling etc. Power Integrity (PI) deals with the power delivery network from a voltage source to active devices (ICs) through boards and packages. The noise in the power distribution network mainly affects the system jitter performance as jitter originates from the varying propagation delay caused by shifting bias levels in active circuits. This phenomenon is more prominent with shrinking technologies. Together this environment causes degradation in signal quality which can be primarily measured either by eye diagram or quantitatively by system Bit error rate.